Job description

## Company: Qualcomm Technologies, Inc. ## Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: Qualcomm's validation team is part of the central Global SoC digital hardware organization responsible for the overall quality of the SoC silicon. The validation team works closely with architects, designers, verification engineers, software engineers, and customers. The team is currently seeking candidate specifically for SOC Infrastructure/NoC, Power and Performance Validation in pre-silicon emulation and post-silicon. The candidate is expected to have an excellent understanding of digital design fundamentals, on-chip interconnects, writing content to validate and analyze SOC bus architecture ,performance and power. Required Skills: * SOC Bandwidth, QoS, Latency and Throughput analysis * Interconnect architectures - NoCs,AXI, AHB etc. Knowledge of upstream and downstream operations and the ability to write programs to stress their transactions for appropriate coverage * Solid expertise in various FIFO designs and related performance/functionality aspects * Come up with thorough performance validation plans and work closely with team members to ensure Performance-Power trade-offs are factored in * System Low power modes * Dynamic clock and voltage scaling operations * Interrupt architecture * Debug architecture - interactions with JTAG based debuggers, state dump scripts * Performance monitor architecture * Thorough understanding of CPU and DDR concepts, Mumtimedia, GPU, Peripheral, * Memory hierarchy and caches - coherency, consistency (ordering), memory types and attributes, synchronization & semaphores, full-system concurrency, MTE, MPAM * Experience in embedded systems/expertise in C, C++, Python and assembly languages * Design and Implementation of drivers and test content * Debugging low level software and hardware issues * Fundamental understanding of Static, Leakage and Dynamic power in a semiconductor design * Familiarity in debug tools including JTAG and kernel debuggers * Structured program development concepts * Logical thinking and problem-solving ability with focus on Power, Performance and SoC System feature validation * Experience leveraging Generative AI technologies for optimizing workflows Minimum Qualifications: • Bachelor's degree in Science, Engineering, or related field and 5+ years of ASIC Design, Validation, Verification, or related work experience. OR Master's degree in Science, Engineering, or related field and 4+ years of ASIC Design, Validation, Verification, or related work experience. OR PhD in Science, Engineering, or related field and 3+ years of ASIC Design, Validation, Verification, or related work experience. Minimum Qualifications: • Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field. Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. Pay range and Other Compensation & Benefits: $121,800.00 - $182,600.00 The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link. If you would like more information about this role, please contact Qualcomm Careers.

Requirements

Must-haves

Qualcomm Technologies, Inc.
Engineering Group, Engineering Group > ASICS Engineering
The candidate is expected to have an excellent understanding of digital design fundamentals, on-chip interconnects, writing content to validate and analyze SOC bus architecture ,performance and power.
SOC Bandwidth, QoS, Latency and Throughput analysis
Interconnect architectures - NoCs,AXI, AHB etc. Knowledge of upstream and downstream operations and the ability to write programs to stress their transactions for appropriate coverage
Solid expertise in various FIFO designs and related performance/functionality aspects
Come up with thorough performance validation plans and work closely with team members to ensure Performance-Power trade-offs are factored in
System Low power modes
Dynamic clock and voltage scaling operations
Interrupt architecture
Debug architecture - interactions with JTAG based debuggers, state dump scripts
Performance monitor architecture
Thorough understanding of CPU and DDR concepts, Mumtimedia, GPU, Peripheral,
Memory hierarchy and caches - coherency, consistency (ordering), memory types and attributes, synchronization & semaphores, full-system concurrency, MTE, MPAM
Experience in embedded systems/expertise in C, C++, Python and assembly languages
Design and Implementation of drivers and test content
Debugging low level software and hardware issues
Fundamental understanding of Static, Leakage and Dynamic power in a semiconductor design
Familiarity in debug tools including JTAG and kernel debuggers
Structured program development concepts
Logical thinking and problem-solving ability with focus on Power, Performance and SoC System feature validation
Experience leveraging Generative AI technologies for optimizing workflows
Bachelor's degree in Science, Engineering, or related field and 5+ years of ASIC Design, Validation, Verification, or related work experience.
Master's degree in Science, Engineering, or related field and 4+ years of ASIC Design, Validation, Verification, or related work experience.

Nice-to-haves

None flagged.

Application prep

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Keywords to mirror

pythonairest

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