Job description

In this job, you will be responsible for RTL coding of blocks specified by you or others for advanced mixed signal circuits. You will be writing detailed design specification and will be in close collaboration with the system architect, circuit designers and design verification engineers.Formal tools like LINT, CDC,RDC will be used to guarantee RTL quality. Supporting design verification to ensure bug free silicon. Working with the PD team for timing closure for your designs and finally supporting silicon bring up Bachelor's of Science in Electric Engineering with 10+ years of relevant experience preferred Deep knowledge of RTL design Deep knowledge of Verilog and System Verilog Good knowledge of Mixed signal concepts Good knowledge of Algorithm development Working experience with physical design teams Good Knowledge of front-end tools (Verilog simulators, linters, clock domain crossing checkers) Good knowledge of synthesis, static timing , DFT is a plus Good knowledge of System-Verilog assertions, checkers and other design verification techniques are a plus Good knowledge of scripting languages. Perl and Python are plusses. Good communication and presentation skills

Requirements

Must-haves

Deep knowledge of RTL design
Deep knowledge of Verilog and System Verilog
Good knowledge of Mixed signal concepts
Good knowledge of Algorithm development
Working experience with physical design teams
Good Knowledge of front-end tools (Verilog simulators, linters, clock domain crossing checkers)
Good knowledge of scripting languages. Perl and Python are plusses.
Good communication and presentation skills

Nice-to-haves

Bachelor's of Science in Electric Engineering with 10+ years of relevant experience preferred
Good knowledge of synthesis, static timing , DFT is a plus
Good knowledge of System-Verilog assertions, checkers and other design verification techniques are a plus

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

python

Platform: apple
Effort: medium