Job description

Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering ( SCHIE ) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for engineers to help achieve that mission. The Compute Silicon & Manufacturing Engineering ( CSME ) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantages to Microsoft and enable our customers to achieve more. As Microsoft's cloud business continues to grow, the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Fabric IP Design team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for experienced engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for a Fabric IP Designer to join the team to support our mission. #SCHIE #CSME Responsibilities The candidate for this position will be expected and able to complete the following responsibilities: • Be part of a design team developing advanced components of the memory sub-system • Develop automation and AI based solutions to improve organizational efficiency • Own design blocks within complex, coherent fabrics, and bridge IPs • Be responsible for all aspects of the design flow including RTL coding, Lint, CDC, timing closure, etc • Collaborate with team members to define interfaces and make optimal design choices • Work with verification teams to develop test plans and ensure functional correctness • Interface with performance modeling, physical design, design for test, and other teams to optimize tradeoffs Qualifications Required Qualifications: • Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 2+ years technical engineering experience OR equivalent experience. Screening Requirements: • Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. • This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. Preferred Qualifications: • 5+ years of related technical engineering experience • OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience or internship experience • OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ year(s) technical engineering experience or internship experience. • OR Doctorate degree in Electrical Engineering, Computer Science, Computer Engineering, or related field • 3+ years of digital logic design experience for ASIC or FPGA. • Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting, etc). • Demonstrated proficiency in Computer Architecture, Digital Design, CPU/SoC design principles as part of CPU, SoC and/or IP development • Demonstrated experience and knowledge of design clock crossings and power/UPF. • Ability to write scripts using Perl, Tcl, Python etc. • Experience using generative AI technologies, agent/skill development • Experience in building and integrating any of the IPs such as protocol bridges, PCIe, cache controllers, memory controllers and DDR, security engines. • Experience in building functional fabrics using Coherent and Non-Coherent protocols. • Familiarity with Industry standard interface protocols such as AXI or CHI. • Familiarity with Synthesis and STA tools. • Good verbal and written communication skills. Silicon Engineering IC3 - The typical base pay range for this role across the U.S. is USD $102,100 - $202,200 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $133,800 - $219,200 per year. Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: careers.microsoft.com This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled. Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

Requirements

Must-haves

We are looking for a Fabric IP Designer to join the team to support our mission.
The candidate for this position will be expected and able to complete the following responsibilities:
Be part of a design team developing advanced components of the memory sub-system
Develop automation and AI based solutions to improve organizational efficiency
Own design blocks within complex, coherent fabrics, and bridge IPs
Be responsible for all aspects of the design flow including RTL coding, Lint, CDC, timing closure, etc
Collaborate with team members to define interfaces and make optimal design choices
Work with verification teams to develop test plans and ensure functional correctness
Interface with performance modeling, physical design, design for test, and other teams to optimize tradeoffs
OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ year(s) technical engineering experience or internship experience.
3+ years of digital logic design experience for ASIC or FPGA.
This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.

Nice-to-haves

OR Doctorate degree in Electrical Engineering, Computer Science, Computer Engineering, or related field
Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting, etc).
Demonstrated proficiency in Computer Architecture, Digital Design, CPU/SoC design principles as part of CPU, SoC and/or IP development
Demonstrated experience and knowledge of design clock crossings and power/UPF.
Ability to write scripts using Perl, Tcl, Python etc.
Experience using generative AI technologies, agent/skill development
Experience in building and integrating any of the IPs such as protocol bridges, PCIe, cache controllers, memory controllers and DDR, security engines.
Experience in building functional fabrics using Coherent and Non-Coherent protocols.
Familiarity with Industry standard interface protocols such as AXI or CHI.
Familiarity with Synthesis and STA tools.
Good verbal and written communication skills.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:

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