In this role, you'll be responsible for the following:
- Building and maintaining Palladium emulation environments, including compile flows, netlist preparation, memory modeling, and clock/reset configurations.
- System-level debug and root cause analysis of complex hardware issues on the emulation platform.
- IP-level debug and validation, working closely with IP owners to isolate and resolve design issues.
- Development and implementation of automation aids, flows, and scripts to improve Palladium build efficiency, debug turnaround, and platform utilization.
- Performance profiling and optimization of emulation models to maximize execution speed.
- Collaboration with multi-disciplinary groups to make sure emulation deliverables are on schedule and support critical program milestones.
BS and a minimum of 10 years relevant industry experience
Proven experience with Cadence Palladium (or equivalent emulation platforms such as Synopsys ZeBu), including build flows, compile optimization, and platform bring-up
Strong debugging skills with experience in system-level and IP-level debug on emulation platforms
Experience with emulation compile flows, including synthesis for emulation, memory compilation, clock modeling, and I/O abstraction
Proficiency in debug tools and methodologies (waveform analysis, signal probing, assertion-based debug, transactors)
Solid understanding of RTL design concepts, SoC architectures, ARM-based subsystems, and standard bus protocols (AXI, AHB, APB)
Experience developing and maintaining automation scripts (Python, Tcl, Perl, Shell) to streamline emulation workflows
Strong analytical and problem-solving skills with ability to debug complex system-level issues
Experience with Wireless SoC applications (Wi-Fi, Bluetooth, cellular) - strongly preferred
Excellent communication and collaboration skills to work effectively across functional teams
Experience with version control systems (Git, Perforce) and CI/CD integration for emulation flows