Job description

Hello Gerald, We are sourcing for Pre-Silicon Verification Engineer with one of our Direct Client in Santa Clara, CA. Please go through to the job description below and of you feel comfortable with the Required skills and responsibilities, please reply me back with your updated word doc resume and Table with your details to vinay.shrivas AT sumerusolutions.com or contact me for more details at 571-250-5780. Project Details: Job Title : Pre-Silicon Verification Engineer Client Location : Santa Clara, CA Project Duration : Long term (6 – 12 + months Contract ) Responsibilities 1) Pre-silicon Verification expertise 2) SystemVerilog experience 3) Importantly someone who is familiar with power management verification (we use SYNP UPF flow). 4) This person should be able to work in Santa Clara and ASAP (preferably next week itself). Submission Candidate Name Present location (city, state or ZIP) Preferred Base Location Work Authorization Tel No Email ID *Joining availability (post-selection) Overall relevant experience of candidate Current Salary Expected Rate/Salary - $$/HR/K Do you have 4 year degree (Y/N) Ready to Travel (Y/N) Where would you stand in scale of 1-10 for this req Additional qualifications include: - Strong SOC/CPU microarchitecture and/or system level skills with five to seven years of pre-si verification background - Experience with logic design and validation tools and methodologies including: Verilog, System Verilog, OVM/UVM, Synopsys VCS - Familiarity of power management flows - Knowledge of assertion based languages and/or methodology and C/C++ would be an added advantage - Knowledge of emulation platforms a plus - Experience in automation using Perl is desirable - Demonstrate capability to ramp on any Industry standard device protocols and architecture - Need to have demonstrated excellence in problem solving and resolution through innovative methods in environment/tools capabilities, test plan and test development, debug, automation, etc. All your information will be kept confidential according to EEO guidelines.

Requirements

Must-haves

Hello Gerald,
Job Title : Pre-Silicon Verification Engineer
Client Location : Santa Clara, CA
Project Duration : Long term (6 – 12 + months Contract )
Pre-silicon Verification expertise
SystemVerilog experience
Importantly someone who is familiar with power management verification (we use SYNP UPF flow).
This person should be able to work in Santa Clara and ASAP (preferably next week itself).
Candidate Name
Present location (city, state or ZIP)
Work Authorization
Joining availability (post-selection)
Overall relevant experience of candidate
Current Salary
Expected Rate/Salary - $$/HR/K
Do you have 4 year degree (Y/N)
Ready to Travel (Y/N)
Where would you stand in scale of 1-10 for this req
Strong SOC/CPU microarchitecture and/or system level skills with five to seven years of pre-si verification background
Experience with logic design and validation tools and methodologies including: Verilog, System Verilog, OVM/UVM, Synopsys VCS
Familiarity of power management flows
Knowledge of assertion based languages and/or methodology and C/C++ would be an added advantage

Nice-to-haves

Preferred Base Location
Knowledge of emulation platforms a plus

Application prep

Use the role’s language and application details while tailoring your materials.

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Effort: medium