Job description

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Role Overview Broadcom’s Central Engineering Group is seeking an I/O Design Engineer with experience in analog and mixed-signal IC design. The candidate will contribute to the design and verification of a broad range of IP and I/Os, including leading-edge AI programs on advanced nodes. Joining a world-class team of engineers with a highly collaborative culture, the role offers opportunities for growth and development. Responsibilities Design of CMOS I/O, high-precision bandgap references, op-amps, comparators and power-on-reset circuits. Run simulations to validate AC/DC performance, signal integrity, jitter and power. Perform transistor reliability and EMIR analysis. Work closely with layout teams to oversee physical design and verification. Build Verilog, Synopsys Liberty and IBIS models. Create and maintain detailed technical documentation, including datasheets, application notes and integration guides. Support chip-level integration and silicon bring-up in test chips and customer products. Technical Skills and Requirements MS or PhD in Electrical Engineering. 6 years of I/O or analog circuit design experience. Deep proficiency in Cadence Virtuoso Schematic/Layout capture and SPICE/Spectre circuit simulation. Solid foundation in I/O protocols including GPIO, I2C, I3C, eMMC, RGMII and SPMI. Familiarity with ESD, Latch-up, EMI and Signal Integrity. Experience with advanced CMOS FinFET and GAA process nodes, including features, technology limitations and PPA tradeoffs. Compensation and Benefits The annual base salary range for this position is USD 109,700.00 To USD 175,500.00 As a valued member of our team, you ll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company s growth. All subject to relevant plan documents and award agreements. Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence. Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law. If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Requirements

Must-haves

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Design of CMOS I/O, high-precision bandgap references, op-amps, comparators and power-on-reset circuits.
Run simulations to validate AC/DC performance, signal integrity, jitter and power.
Perform transistor reliability and EMIR analysis.
Work closely with layout teams to oversee physical design and verification.
Build Verilog, Synopsys Liberty and IBIS models.
Create and maintain detailed technical documentation, including datasheets, application notes and integration guides.
Support chip-level integration and silicon bring-up in test chips and customer products.
Technical Skills and Requirements
MS or PhD in Electrical Engineering.
6 years of I/O or analog circuit design experience.
Deep proficiency in Cadence Virtuoso Schematic/Layout capture and SPICE/Spectre circuit simulation.
Solid foundation in I/O protocols including GPIO, I2C, I3C, eMMC, RGMII and SPMI.
Familiarity with ESD, Latch-up, EMI and Signal Integrity.
Experience with advanced CMOS FinFET and GAA process nodes, including features, technology limitations and PPA tradeoffs.

Nice-to-haves

None flagged.

Application prep

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Keywords to mirror

Platform: workday
Effort: long

Benefits

Benefits detected in the listing.

Dental

Vision

401(K)