SoC Physical Design Verification Engineer
Apple· Consumer Technology· May 28, 2026 · 5mo agoPosted 152 days ago
Beaverton, Oregon, United States · San Jose, California, United States
In office
Full-time
Junior
$129K–$195K
Before you apply
Ghost Signal:
Open since May 28, 2026 — 152 days, and still accepting applications.
Job description
• As a member of our physical design team, you will perform various types of physical verification checks such as LVS, DRC, design-for-manufacturing & design-for-yield, and lithography at the chip and block level.
• You will collaborate with the CAD/Technology teams for flow bring up and validation. We work directly with the implementation team during the entire chip design cycle to drive signoff closure for tapeout.
• You will lead schedules and support cross-functional engineering efforts.
• You will work on padring, bump, RDL design, and working with the package and floorplan teams.
BS degree with 0 years of relevant industry experience.
Experienced with physical verification flows such as DRC/LVS/ANT and layout integration methodology
Understands RTL to GDS physical design flow
Scripting skills to debug flow related issues and make enhancements as appropriate
Experienced in industry standard tools used for physical verification such as Mentor Calibre, Synopsys ICV, etc
Layout design background and experience a plus
Application prep
Use the role’s language and application details while tailoring your materials.
- Platform
- apple
- Effort
- medium