Job description

For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal processing. Our rockstar team thrives on solving complex challenges with innovative end-user solutions for the world's top consumer brands. Cirrus Logic is also known for its award-winning culture, which was built on a foundation of inclusion and fairness, meaningful community engagement, and delivering enjoyable employee experiences at every turn. But we couldn’t do it without our extraordinary workforce – and that’s where you come in. Join our team and help us continue to make Cirrus Logic an exceptional place to grow your career! We are seeking highly motivated digital design interns to join our team to work on Cirrus Logic's newest mixed-signal integrated circuits (ICs) products. In this role, you’ll contribute to the development of digital logic circuits such as digital filters for a wide range of applications, Mixed-Signal Audio, Embedded SoCs, and high-precision Industrial/Data Acquisition systems. This is a hands-on opportunity to work in a collaborative, innovation-driven environment where your contributions will directly impact real-world products. We recruit interns year-round for Spring, Summer, and Fall 2027 opportunities. Each internship lasts 12–16 weeks and follows a full-time schedule. Responsibilities Design and implement RTL modules using Verilog for DSP and data conversion ICs. Perform logic simulation, functional verification, and synthesis in a mixed-signal environment. Collaborate with the design team on integration and system-level verification. Support behavioral modeling of analog and mixed-signal circuits. Assist with test vector generation and lab test development. Required Skills and Qualifications Currently pursuing a MS or PhD in Electrical Engineering or a related field. Strong understanding of Digital Signal Processing (DSP) concepts. Proficiency in Verilog and Synopsys-based design flows. Experience with Matlab for algorithm development and analysis. Familiarity with PWM techniques, transistor-level simulators, and place-and-route tools. Cirrus Logic follows a 2+ day in-office work schedule but interns should expect to be in the office more often, up to 5 days per week, based on business needs and team preference. Interns must be based within commutable distance of the work location listed on the job posting, or willing to relocate prior to beginning their internship with Cirrus Logic. Export control restrictions based upon applicable laws and regulations would prohibit candidates who are nationals of certain embargoed countries from working in this position without Cirrus Logic first obtaining an export license. Candidates for this role must be able to access technical data without a requirement for an export license. We are unable to sponsor or obtain export licenses for this role. Cirrus Logic strives to select the best qualified applicant for any opening. Different approaches, ideas and points of view are both valued and respected. Employment decisions are made on the basis of job-related criteria without regard to race, color, religion, sex, national origin, age, protected veteran or disabled status, genetic information, or any other classification protected by applicable law.

Requirements

Must-haves

Design and implement RTL modules using Verilog for DSP and data conversion ICs.
Perform logic simulation, functional verification, and synthesis in a mixed-signal environment.
Collaborate with the design team on integration and system-level verification.
Support behavioral modeling of analog and mixed-signal circuits.
Assist with test vector generation and lab test development.
Required Skills and Qualifications
Currently pursuing a MS or PhD in Electrical Engineering or a related field.
Strong understanding of Digital Signal Processing (DSP) concepts.
Proficiency in Verilog and Synopsys-based design flows.
Experience with Matlab for algorithm development and analysis.
Familiarity with PWM techniques, transistor-level simulators, and place-and-route tools.

Nice-to-haves

None flagged.

Application prep

Use the role’s language and application details while tailoring your materials.

Platform: lever
Effort: quick