Job description

The Rad Hard Precision Design Group is seeking an experienced mask designer to join the team in either the Research Triangle Park, NC or the Palm Bay, FL locations. The purpose of this position is to create top-level and cell-level layouts for our Rad Hard product development team targeted toward Space markets. The Rad Hard developments include power management products, precision analog products and digital core layouts along with digital library development for new process variants. The candidate will utilize the Cadence tool set and requires interaction with circuit designers, layout designers, and CAD team. Responsibilities: • Work at multiple levels of hierarchy from top-level layout floor planning to macro/block level routing • Work closely with circuit designers to build physical design floorplan and create package bond diagrams • Create high performance custom analog and mixed signal cell layout and verification • Complete the physical layout design with the constraints of circuit design requirements • Verify the physical layout design to meet both circuit design requirements and process requirements • Execute mask data release and archiving • Use new tools and methods and work with CAD/CAE to improve layout design quality and efficiency • Minimum fifteen years experience working with analog, power or mixed signal IC layouts • A good working knowledge of IC layout methodologies, flows and CAD tools such as Cadence virtuoso layout physical verification • Basic understanding of electronic principles dealing with circuit and layout design • Previous experience with BCD and SOI processes. • Good communication skills • Familiar with device physics is preferred Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier . With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future. At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives. We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process. Are you ready to join our team and shape the future with us? Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement . Renesas Electronics deals with dual-use technology that is subject to U.S. export controls regulations. Under these regulations it may be necessary for Renesas to obtain U.S. government export license prior to release of technology to certain persons. The decision whether or not to file or pursue an export license application is at the sole discretion of Renesas.

Requirements

Must-haves

Work at multiple levels of hierarchy from top-level layout floor planning to macro/block level routing
Work closely with circuit designers to build physical design floorplan and create package bond diagrams
Create high performance custom analog and mixed signal cell layout and verification
Complete the physical layout design with the constraints of circuit design requirements
Verify the physical layout design to meet both circuit design requirements and process requirements
Execute mask data release and archiving
Use new tools and methods and work with CAD/CAE to improve layout design quality and efficiency
Minimum fifteen years experience working with analog, power or mixed signal IC layouts
A good working knowledge of IC layout methodologies, flows and CAD tools such as Cadence virtuoso layout physical verification
Basic understanding of electronic principles dealing with circuit and layout design
Previous experience with BCD and SOI processes.
Good communication skills
We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.
Are you ready to join our team and shape the future with us?

Nice-to-haves

Familiar with device physics is preferred

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

agile

Platform: smartrecruiters
Effort: medium