Job description

You’ll be responsible for pre-silicon RTL verification at the block, subsystem, and top-level SOC, taking your scope from test planning through coverage closure and signoff. Working closely with architects, designers, and firmware engineers, you’ll build reusable testbenches and verification environments using modern, metric-driven methodology. Areas you may work on include the Power Management Unit, CPU subsystem, DMA, on-chip debug infrastructure, PCIe, bus fabric, boot and secure-boot sequencing, MAC-PHY Verification, Radio integration, and peripherals such as SPI — choosing simulation, formal, or whichever approach the design actually calls for. Low power is part of your scope wherever it shows up: you’ll verify power intent using UPF within your area. Over time, you can grow deeper into the IPs and subsystems you know best, or broader — across IPs and up from block level to full SOC integration. The team is also pushing hard on AI-assisted verification, and you’ll help figure out where it fits best: test generation, debug, coverage closure, or all the above. BS and a minimum of 10 years relevant industry experience. Hands-on experience across the verification cycle: test planning, testbench implementation, test creation and debug, and coverage closure. Strong SystemVerilog and Verilog skills, with solid working knowledge of UVM. Solid problem-solving and debugging skills with constrained-random verification. Understanding of digital logic design, SOC architecture, and microarchitecture. Experience taking at least one ASIC/SOC from concept through tape-out. Verification experience with PCIe, bus fabric/NOC, or AHB/AXI-based architectures in a UVM environment. Experience verifying IP or top-level integration for a WiFi or Bluetooth SOC, or knowledge of wireless protocols. Experience with low-power verification, UPF, boot-up, power-cycling, and HW/FW interaction. Experience with SystemVerilog Assertions (SVA) and/or formal tools (e.g., JasperGold). Experience defining coverage space and writing coverage models. Experience with embedded CPU verification; programming in C/C++ or assembly. Scripting in Python or Perl; interest in applying AI/ML to verification workflows Great teammate with excellent communication skills and the desire to take on diverse challenges.

Requirements

Must-haves

BS and a minimum of 10 years relevant industry experience.
Hands-on experience across the verification cycle: test planning, testbench implementation, test creation and debug, and coverage closure.
Strong SystemVerilog and Verilog skills, with solid working knowledge of UVM.
Solid problem-solving and debugging skills with constrained-random verification.
Understanding of digital logic design, SOC architecture, and microarchitecture.
Experience taking at least one ASIC/SOC from concept through tape-out.
Verification experience with PCIe, bus fabric/NOC, or AHB/AXI-based architectures in a UVM environment.
Experience verifying IP or top-level integration for a WiFi or Bluetooth SOC, or knowledge of wireless protocols.
Experience with low-power verification, UPF, boot-up, power-cycling, and HW/FW interaction.
Experience with SystemVerilog Assertions (SVA) and/or formal tools (e.g., JasperGold).
Experience defining coverage space and writing coverage models.
Experience with embedded CPU verification; programming in C/C++ or assembly.
Scripting in Python or Perl; interest in applying AI/ML to verification workflows
Great teammate with excellent communication skills and the desire to take on diverse challenges.

Nice-to-haves

None flagged.

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

aipythonml

Platform: apple
Effort: medium