Job description

Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the AI Silicon Architecture team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for a Principal AI Silicon Architect to join the team. #SCHIE Responsibilities • Own end-to-end power architecture for high-power AI accelerator SoCs, including tradeoff analysis not only for SOC, but expand to package, board, and system. • Define SoC and package-level power-management architecture, including power/voltage domains, DVFS, clock and power gating, low-power states, workload-aware power management, and other power-saving mechanisms. • Define architectures for high-power operating conditions, including management of workload power excursions, peak power, sustained power, transient behavior, and power/thermal constraints. • Partner with performance and workload teams to understand workload characteristics and identify opportunities to maximize performance per watt and system-level efficiency. Drive architectural tradeoffs across performance, power, power-delivery capability, thermal limits, reliability, area, cost, and implementation complexity. • Translate workload and product requirements into system and silicon-level power budgets, design targets, and architectural requirements. • Define the SoC-to-system interfaces and control mechanisms for power, thermal, and platform management. • Work closely with SoC architecture, physical design, package, board/system, power delivery, thermal, firmware, platform, manufacturing, and validation teams from early architecture through product deployment. • Provide technical leadership throughout the development lifecycle, including architecture specification, design reviews, implementation tradeoffs, silicon bring-up, characterization, and optimization. Qualifications Required/minimum qualifications • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 7+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 10+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 12+ years technical engineering experience OR equivalent experience. Other Requirements: • Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. • This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations.    As a condition of employment, the successful candidate will be required   to provide either proof of their country of citizenship or proof of their US. residency or other protected status   (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information.   To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.   Preferred Qualifications: • Significant industry experience in SoC power architecture, power delivery, power management, power integrity, or closely related areas, with experience on high-performance/high-power SoCs. • Demonstrated experience architecting and optimizing power delivery across multiple levels of the system, including silicon/SoC, package, board, and power supply. • Demonstrated ability to make complex architectural tradeoffs involving performance, power, thermal, reliability, cost, and implementation complexity. • Deep knowledge of high-power SoC power-delivery architecture, including package and board PDN design and optimization. • Deep understanding of power integrity, voltage droop, transient response, current delivery, power rails/domains, and the interaction between workload behavior and PDN design. • Experience defining package-level and SoC-level power architecture for large, high-performance silicon. • Understanding of voltage/frequency scaling, DVFS, clock gating, power gating, power states, workload-aware power management, and energy-efficiency optimization. • Experience with silicon/package/board co-design and the ability to make system-level rather than locally optimal power decisions. • Experience with AI accelerators, GPUs, HPC processors, server CPUs, or other very high-power datacenter-class silicon. • Experience analyzing workload power characteristics and translating them into power-delivery and power-management requirements. • Experience with multi-die or chiplet architectures and managing power across multiple dies and power rails. • Understanding of the interaction between power delivery, thermal design, reliability, performance, and system design. • Proven ability to influence architecture across organizational boundaries and communicate complex tradeoffs to both implementation teams and senior technical leadership. Silicon Engineering IC6 - The typical base pay range for this role across the U.S. is USD $165,600 - $296,400 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $220,800 - $331,200 per year. Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: careers.microsoft.com This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled. Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

Requirements

Must-haves

We are looking for a Principal AI Silicon Architect to join the team.
Own end-to-end power architecture for high-power AI accelerator SoCs, including tradeoff analysis not only for SOC, but expand to package, board, and system.
Define SoC and package-level power-management architecture, including power/voltage domains, DVFS, clock and power gating, low-power states, workload-aware power management, and other power-saving mechanisms.
Define architectures for high-power operating conditions, including management of workload power excursions, peak power, sustained power, transient behavior, and power/thermal constraints.
Translate workload and product requirements into system and silicon-level power budgets, design targets, and architectural requirements.
Define the SoC-to-system interfaces and control mechanisms for power, thermal, and platform management.
Work closely with SoC architecture, physical design, package, board/system, power delivery, thermal, firmware, platform, manufacturing, and validation teams from early architecture through product deployment.
Provide technical leadership throughout the development lifecycle, including architecture specification, design reviews, implementation tradeoffs, silicon bring-up, characterization, and optimization.
Required/minimum qualifications
This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.

Nice-to-haves

Significant industry experience in SoC power architecture, power delivery, power management, power integrity, or closely related areas, with experience on high-performance/high-power SoCs.
Demonstrated experience architecting and optimizing power delivery across multiple levels of the system, including silicon/SoC, package, board, and power supply.
Demonstrated ability to make complex architectural tradeoffs involving performance, power, thermal, reliability, cost, and implementation complexity.
Deep knowledge of high-power SoC power-delivery architecture, including package and board PDN design and optimization.
Deep understanding of power integrity, voltage droop, transient response, current delivery, power rails/domains, and the interaction between workload behavior and PDN design.
Experience defining package-level and SoC-level power architecture for large, high-performance silicon.
Understanding of voltage/frequency scaling, DVFS, clock gating, power gating, power states, workload-aware power management, and energy-efficiency optimization.
Experience with silicon/package/board co-design and the ability to make system-level rather than locally optimal power decisions.
Experience with AI accelerators, GPUs, HPC processors, server CPUs, or other very high-power datacenter-class silicon.
Experience analyzing workload power characteristics and translating them into power-delivery and power-management requirements.
Experience with multi-die or chiplet architectures and managing power across multiple dies and power rails.
Understanding of the interaction between power delivery, thermal design, reliability, performance, and system design.

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azureai

Platform: eightfold
Effort: medium

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