Job description

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Marvell Advanced Packaging team is responsible for package design and technology development to meet the electrical, mechanical, thermal, and system requirements of next-generation High-Performance Computing (HPC), Artificial Intelligence (AI), and networking solutions. The team focuses on signal integrity, power integrity, thermal integrity, mechanical integrity, processability, manufacturability, and reliability. This work involves high-speed signaling and complex power delivery networks (PDNs) that require innovative and customized solutions to meet constantly evolving customer needs. Many of these new designs require multi-chip, multi-component configurations, including but not limited to 2.5D and 3D packages, co-packaged copper or optical solutions, and advanced substrates. Marvell has partnered with the world's leading manufacturers to solve our customers' most challenging design and integration problems through industry-leading packaging technologies. What You Can Expect Lead small project teams of design and simulation engineers to deliver innovative, high-quality packaging solutions. Drive package definition and architecture development for performance-line products utilizing cutting-edge packaging technologies. Interface with package suppliers to select appropriate packaging technologies and ensure manufacturability, while meeting performance, reliability, and cost requirements. What We re Looking For Extensive experience in substrate and/or board design for advanced packaging technologies. Solid understanding of design-for-manufacturing (DFM) and reliability principles, as well as electrical performance considerations, with the ability to make appropriate trade-off decisions. Proven ability to lead complex package architecture development projects involving relevant internal stakeholders, external partners, and customers. Expertise in industry-standard tools and workflows, including Cadence 3DIC, ISP, APD, and SiP. Bachelor s degree in Electrical Engineering or a related field with 5 years of relevant professional experience; Master s degree or Ph.D. with 3 years of relevant professional experience. Skills Needed to Be Successful in This Role Innovative thinking and a fundamental understanding of design rules, breakout, placement and routing, signal shielding, reference planes, power distribution, and pinout development while considering overall package and system requirements. Experience with current-generation HBM, DDR, SerDes, D2D, D2H, ADC, DAC, PCIe, Ethernet, and related technologies. Strong understanding of signal and power integrity across substrate, board, package, and system levels. Understanding of advanced 2.5D and 3D packaging technologies, including: CoWoS-S/R/L EMIB CPO CPC Familiarity with tools and workflows such as Cadence Sigrity, Clarity, Innovus, Virtuoso, Ansys, AutoCAD, and SolidWorks. Experience contributing to tool, process, and workflow development, as well as library maintenance. Experience collaborating with chip design and electrical simulation teams to optimize designs. Familiarity with running and interpreting signal and power integrity simulations is a plus. Ability to manage programs involving cross-functional teams. Strong interpersonal skills, a willingness to learn, and the ability to work effectively with stakeholders across multiple global time zones are essential. Strong communication, presentation, and documentation skills. Expected Base Pay Range (USD) 142,700 - 211,230, $ per annum The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. This role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success. Additional Compensation and Benefit Elements Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps marvell.com . Interview Integrity To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-SA1

Requirements

Must-haves

Familiarity with tools and workflows such as Cadence Sigrity, Clarity, Innovus, Virtuoso, Ansys, AutoCAD, and SolidWorks.
Experience contributing to tool, process, and workflow development, as well as library maintenance.
Ability to manage programs involving cross-functional teams. Strong interpersonal skills, a willingness to learn, and the ability to work effectively with stakeholders across multiple global time zones are essential.
Strong communication, presentation, and documentation skills.
142,700 - 211,230, $ per annum
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps marvell.com .
Interview Integrity

Nice-to-haves

Experience collaborating with chip design and electrical simulation teams to optimize designs. Familiarity with running and interpreting signal and power integrity simulations is a plus.

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

Platform: workday
Effort: long