Job description

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Artificial intelligence will be one of humanity’s most transformative inventions. At Google DeepMind, we are a pioneering AI lab with exceptional interdisciplinary teams focused on advancing AI development to solve complex global challenges and accelerate high-quality product innovation for billions of users. We use our technologies for widespread public benefit and scientific discovery, ensuring safety and ethics are always our highest priority. We are pushing the boundaries across multiple domains. Our global teams offer diverse learning opportunities and varied career pathways for those driven to achieve exceptional results through collective effort. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $217000 - $236000 (USD) + 15% bonus target Learn more about benefits at Google . • Architect advanced technology node power solutions and establish use case budgets with block and full-chip estimations. • Lead and drive the automation and integration of power analysis processes—including RTL power analysis, optimization, IP selection, physical design, and timing closure—into our automated flow. • Apply hardware expertise to build, create, and integrate software components for automated early- and late-stage power analysis and optimization. • Partner with systems power and cross-functional teams to define, execute, and advocate for power management and reduction methodologies from SoC architecture through sign-off. • Specify requirements for power management IPs while managing their design, integration, and post-silicon validation. • 7 years of experience working in ASIC power analysis & optimization, including experience with production chips • Experience in tape-outs of chips • Experience interacting and collaborating with silicon foundries and other external vendors for the tapeout process • Experience with Verilog and industry-standard EDA tools for power analysis & optimization design (e.g., PP-RTLA, PowerArtist, PrimeTime-PX, PrimeTime, Cadence Innovus, Synopsys Fusion Compiler) • Experience with scripting languages (e.g., Perl, Tcl) for automation of power analysis & optimization flows • Software development experience Minimum qualifications: • 7 years of experience working in ASIC power analysis & optimization, including experience with production chips • Experience in tape-outs of chips • Experience interacting and collaborating with silicon foundries and other external vendors for the tapeout process • Experience with Verilog and industry-standard EDA tools for power analysis & optimization design (e.g., PP-RTLA, PowerArtist, PrimeTime-PX, PrimeTime, Cadence Innovus, Synopsys Fusion Compiler) • Experience with scripting languages (e.g., Perl, Tcl) for automation of power analysis & optimization flows • Software development experience Preferred qualifications: • Master's degree or PhD in Electrical Engineering, Physics or related field

Requirements

Must-haves

We are pushing the boundaries across multiple domains. Our global teams offer diverse learning opportunities and varied career pathways for those driven to achieve exceptional results through collective effort.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
Learn more about benefits at Google .
Architect advanced technology node power solutions and establish use case budgets with block and full-chip estimations.
Lead and drive the automation and integration of power analysis processes—including RTL power analysis, optimization, IP selection, physical design, and timing closure—into our automated flow.
Apply hardware expertise to build, create, and integrate software components for automated early- and late-stage power analysis and optimization.
Partner with systems power and cross-functional teams to define, execute, and advocate for power management and reduction methodologies from SoC architecture through sign-off.
Specify requirements for power management IPs while managing their design, integration, and post-silicon validation.
7 years of experience working in ASIC power analysis & optimization, including experience with production chips
Experience in tape-outs of chips
Experience interacting and collaborating with silicon foundries and other external vendors for the tapeout process
Experience with Verilog and industry-standard EDA tools for power analysis & optimization design (e.g., PP-RTLA, PowerArtist, PrimeTime-PX, PrimeTime, Cadence Innovus, Synopsys Fusion Compiler)
Experience with scripting languages (e.g., Perl, Tcl) for automation of power analysis & optimization flows
Software development experience
7 years of experience working in ASIC power analysis & optimization, including experience with production chips
Experience in tape-outs of chips
Experience interacting and collaborating with silicon foundries and other external vendors for the tapeout process
Experience with Verilog and industry-standard EDA tools for power analysis & optimization design (e.g., PP-RTLA, PowerArtist, PrimeTime-PX, PrimeTime, Cadence Innovus, Synopsys Fusion Compiler)
Experience with scripting languages (e.g., Perl, Tcl) for automation of power analysis & optimization flows
Software development experience

Nice-to-haves

US: $217000 - $236000 (USD) + 15% bonus target
Master's degree or PhD in Electrical Engineering, Physics or related field

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

Platform: google
Effort: medium