Job description

Job Details: Job Description: Altera is looking for a Senior Principal Engineer to serve as a key technical leader responsible for defining and advancing FPGA physical synthesis, timing optimization, and implementation methodologies. This individual will bring deep expertise in EDA algorithms, optimization engines, design compilation, and performance-driven implementation technologies. The ideal candidate will have a proven track record of architecting and delivering breakthrough technologies that significantly improve quality of results (QoR), runtime, scalability, and customer productivity for large-scale FPGA or ASIC designs. This role offers the opportunity to influence the long-term technical direction of Altera s FPGA software platform and collaborate with world-class engineers solving some of the industry s most complex optimization challenges. Key Responsibilities Define and drive the architectural roadmap for FPGA compiler technologies. Design and develop advanced optimization algorithms focused on timing closure, area reduction, power optimization, routability, and runtime improvement. Lead development of next-generation timing driven optimization methodologies. Architect scalable solutions for large hierarchical designs and complex FPGA implementation flows. Drive innovation across synthesis, placement, routing, timing analysis, and physical optimization domains. Partner with cross-functional engineering teams to integrate new technologies into production tool flows. Analyze customer workloads, benchmark results, and field feedback to identify high-impact improvement opportunities. Lead technical investigations of challenging timing and implementation problems across customer designs. Mentor engineers and provide technical leadership across architectural and algorithmic initiatives. Collaborate with product management and strategic customers to translate market needs into differentiated technology solutions. Contribute to patents, publications, and industry-leading innovations that strengthen Altera s competitive position. The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance. $231.5K - $304.5K USD We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations. Qualifications: Minimum Qualifications BS, MS, or PhD in Electrical Engineering, Computer Science, Computer Engineering, or a related technical field. 15 years of experience developing EDA software, FPGA tools, ASIC implementation tools, or related optimization technologies. Deep expertise in one or more of the following domains: Physical Synthesis Timing Analysis Logic Synthesis Placement and Routing Design Optimization Algorithms FPGA Architecture and CAD Flows Static Timing Analysis Physical Design Implementation Demonstrated experience architecting large-scale software systems and optimization engines. Strong software development skills in C , data structures, algorithms, and performance optimization. Proven ability to solve highly complex technical problems and deliver innovative solutions to production software environments. Experience influencing technical direction across multiple engineering teams. Preferred Qualifications Experience developing commercial FPGA or ASIC implementation tools. Expertise in path-based optimization, timing-driven synthesis, or physical design methodologies. Experience improving tool QoR, runtime performance, or scalability for large customer designs. Background creating novel optimization algorithms that became widely adopted production technologies. Experience with machine learning applications for EDA optimization and implementation flows. Patent portfolio or significant technical publications in EDA, FPGA, or semiconductor design. Experience serving as a Distinguished Engineer, Architect, Fellow, or equivalent technical leadership role. What You ll Impact The next generation of Altera FPGA implementation technologies. Core algorithms that directly influence customer design performance and productivity. Strategic roadmap decisions for synthesis, timing closure, and physical optimization. Technical mentorship and engineering excellence across the organization. Innovation that differentiates Altera s FPGA software platform in an increasingly competitive market. At Altera, you ll work alongside elite engineers solving some of the most challenging problems in semiconductor design automation while helping shape the future of programmable computing. Job Type: Regular Shift: Shift 1 (United States of America) Primary Location: San Jose, California, United States Additional Locations: Colorado, United States (Remote) Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Requirements

Must-haves

Define and drive the architectural roadmap for FPGA compiler technologies.
Design and develop advanced optimization algorithms focused on timing closure, area reduction, power optimization, routability, and runtime improvement.
Lead development of next-generation timing driven optimization methodologies.
Architect scalable solutions for large hierarchical designs and complex FPGA implementation flows.
Drive innovation across synthesis, placement, routing, timing analysis, and physical optimization domains.
Partner with cross-functional engineering teams to integrate new technologies into production tool flows.
Analyze customer workloads, benchmark results, and field feedback to identify high-impact improvement opportunities.
Lead technical investigations of challenging timing and implementation problems across customer designs.
Mentor engineers and provide technical leadership across architectural and algorithmic initiatives.
Collaborate with product management and strategic customers to translate market needs into differentiated technology solutions.
Contribute to patents, publications, and industry-leading innovations that strengthen Altera s competitive position.
We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.

Nice-to-haves

Experience developing commercial FPGA or ASIC implementation tools.
Expertise in path-based optimization, timing-driven synthesis, or physical design methodologies.
Experience improving tool QoR, runtime performance, or scalability for large customer designs.
Background creating novel optimization algorithms that became widely adopted production technologies.
Experience with machine learning applications for EDA optimization and implementation flows.
Patent portfolio or significant technical publications in EDA, FPGA, or semiconductor design.
Experience serving as a Distinguished Engineer, Architect, Fellow, or equivalent technical leadership role.
What You ll Impact
The next generation of Altera FPGA implementation technologies.
Core algorithms that directly influence customer design performance and productivity.
Strategic roadmap decisions for synthesis, timing closure, and physical optimization.
Technical mentorship and engineering excellence across the organization.

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

machine learning

Platform: workday
Effort: long