Job description

## Company: Qualcomm Technologies, Inc. ## Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path. Qualcomm's Global SoC Power team is currently seeking candidate whose primary role is to implement and validate low power design intent requirements at the SoC-level. The candidate will work with frontend RTL, DFT, Synthesis, Design Verification and Physical Design teams during the SoC development. The role also expands to power analysis and projection of SoC Use Case power this may include creating power models and power dashboard for SoC level power targets. The candidate will have the opportunity to work with IP designers, power target (Chipset/SW) teams, and Post-Silicon test teams to jointly ensure power intent design requirements and power projections are fully validated from pre-silicon to silicon and post-silicon power optimization.. Minimum Qualifications: • Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. QUALIFICATIONS: * Bachelor's degree in Electrical or Computer Engineering plus: * ASIC frontend development * Logic design, RTL coding, verification, synthesis, and timing closure * Hardware description languages (Verilog, VHDL, System Verilog) * Power-aware implementation flow, including UPF/CPF/Conformal Low Power Check * Scripting - Perl/Tcl/Python PREFERRED QUALIFICATIONS: * Master's degree in Electrical or Computer Engineering Experience with/in: * Familiarity of overall SoC Infrastructure – DDR, Busses, CPUs, I/Os and DFT Components * Familiarity of power islands, power gating, power sequencing and multi-voltage domain design * Power analysis familiarity in areas of clocktree, peak power, TDP, limits management Responsibilities/Duties: * Work with frontend RTL, DFT, Synthesis, and Physical design teams in the development of power intent design at SoC level * Generate and validate power intent design (UPF) at SoC level * Review designs and guide IP designers' power intent design ensuring it meets SoC level low power implementation requirements * Work with design verification in validating low power design featurs at SoC and IP level. * Collaborate with company CAD and vendor to enhance existing power flows and tools * Improve power design flows in areas of power modeling, clock power analysis, structural power validation, IP power intent QA * Execute power-aware implementation flow, including UPF/CPF/Conformal Low Power Check * Review IP design's power features and power budgets/estimates * Track IP power development through the design cycle ensuring it meets power budgets - leakage/dynamic at every milestone * Perform power analysis/projection of SoC baseline power and deliver SoC power models to chipset * Execute power simulation/analysis -- (PtPx/PowerArtist/Prime Power/PowerPro) Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. Pay range and Other Compensation & Benefits: $145,600.00 - $218,400.00 The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link. If you would like more information about this role, please contact Qualcomm Careers.

Requirements

Must-haves

Qualcomm Technologies, Inc.
Engineering Group, Engineering Group > ASICS Engineering
Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
Bachelor's degree in Electrical or Computer Engineering plus:
ASIC frontend development
Logic design, RTL coding, verification, synthesis, and timing closure
Hardware description languages (Verilog, VHDL, System Verilog)
Power-aware implementation flow, including UPF/CPF/Conformal Low Power Check
Scripting - Perl/Tcl/Python
Familiarity of overall SoC Infrastructure – DDR, Busses, CPUs, I/Os and DFT Components
Familiarity of power islands, power gating, power sequencing and multi-voltage domain design
Power analysis familiarity in areas of clocktree, peak power, TDP, limits management
Work with frontend RTL, DFT, Synthesis, and Physical design teams in the development of power intent design at SoC level
Generate and validate power intent design (UPF) at SoC level
Review designs and guide IP designers' power intent design ensuring it meets SoC level low power implementation requirements
Work with design verification in validating low power design featurs at SoC and IP level.
Collaborate with company CAD and vendor to enhance existing power flows and tools
Improve power design flows in areas of power modeling, clock power analysis, structural power validation, IP power intent QA
Execute power-aware implementation flow, including UPF/CPF/Conformal Low Power Check
Review IP design's power features and power budgets/estimates
Track IP power development through the design cycle ensuring it meets power budgets - leakage/dynamic at every milestone

Nice-to-haves

Master's degree in Electrical or Computer Engineering

Application prep

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