Job description

Waymo is an autonomous driving technology company with the mission to be the world's most trusted driver. Since its start as the Google Self-Driving Car Project in 2009, Waymo has focused on building the Waymo Driver—The World's Most Experienced Driver™—to improve access to mobility while saving thousands of lives now lost to traffic crashes. The Waymo Driver powers Waymo’s fully autonomous ride-hail service and can also be applied to a range of vehicle platforms and product use cases. The Waymo Driver has provided over ten million rider-only trips, enabled by its experience autonomously driving over 100 million miles on public roads and tens of billions in simulation across 15+ U.S. states. Waymo's Compute Team is tasked with a critical and exciting mission: We deliver the compute platform responsible for running the fully autonomous vehicle’s software stack. To achieve our mission, we architect and create high-performance custom silicon; we develop system-level compute architectures that push the boundaries of performance, power, and latency; and we collaborate closely with many other teammates to ensure we design and optimize hardware and software for maximum performance. We are a multidisciplinary team seeking curious and talented teammates to work on one of the world’s highest performance automotive compute platforms. In this hybrid role, you will report to an Engineering Director. You will: Define the architecture and microarchitecture for Waymo's next-generation autonomous vehicle SoCs, translating system-level requirements into detailed hardware specifications and RTL implementation, using your knowledge of how hardware, firmware, drivers, and compilers interact Lead microarchitecture and implementation of IPs and subsystems, including for high-performance cache/memory hierarchies, Network-on-Chip (NoC) interconnects, and custom accelerators Work with Architects, Firmware and Software teams to drive feature closure and develop microarchitecture specifications Perform power, area and performance exploration and optimization of digital designs Mentor other engineers and guide the technical side of relationships with external vendors, using innovative ideas to solve their design challenges, evaluate and select third-party IP, and ensure a timely and successful tapeout and product You have: MS degree in Computer Engineering, Electrical Engineering, or a related field, or equivalent practical experience 10+ years of industry experience in ASIC/SoC digital design, microarchitecture, and integration, including ownership of major design blocks or subsystems Proven track record of technical leadership driving design and execution from concept to production, and hands-on experience with multiple successful ASIC tapeouts Deep expertise in SystemVerilog for RTL design, microarchitecture, and integration Strong understanding of computer architecture, memory systems, cache coherence, and high-speed on-chip interconnects Fluency in programming/scripting languages (e.g., Python, C++) for architectural modeling, design automation, and debug Strong debug and problem-solving skills, with the ability to root-cause complex issues across hardware and software boundaries We prefer: PhD degree in Computer Engineering, Electrical Engineering, or a related field Experience in hardware/software co-design, including in mixed hardware/software datapaths, such as in the context of DSPs, GPUs, and ML accelerators Knowledge of arithmetic units, processor design, accelerators, bus architectures, fabrics/NoC or memory hierarchies. Knowledge of high performance and low power design techniques Fluency and comfort with AI tools to accelerate and improve design and debug Experience with Chisel (Scala) or other hardware DSLs for RTL generation The expected base salary range for this full-time position across US locations is listed below. Actual starting pay will be based on job-related factors, including exact work location, experience, relevant training and education, and skill level. Your recruiter can share more about the specific salary range for the role location or, if the role can be performed remote, the specific salary range for your preferred location, during the hiring process. Waymo employees are also eligible to participate in Waymo’s discretionary annual bonus program, equity incentive plan, and generous Company benefits program, subject to eligibility requirements. Salary Range $251,000 — $310,000 USD

Requirements

Must-haves

In this hybrid role, you will report to an Engineering Director.
Lead microarchitecture and implementation of IPs and subsystems, including for high-performance cache/memory hierarchies, Network-on-Chip (NoC) interconnects, and custom accelerators
Work with Architects, Firmware and Software teams to drive feature closure and develop microarchitecture specifications
Perform power, area and performance exploration and optimization of digital designs
MS degree in Computer Engineering, Electrical Engineering, or a related field, or equivalent practical experience
10+ years of industry experience in ASIC/SoC digital design, microarchitecture, and integration, including ownership of major design blocks or subsystems
Proven track record of technical leadership driving design and execution from concept to production, and hands-on experience with multiple successful ASIC tapeouts
Deep expertise in SystemVerilog for RTL design, microarchitecture, and integration
Strong understanding of computer architecture, memory systems, cache coherence, and high-speed on-chip interconnects
Fluency in programming/scripting languages (e.g., Python, C++) for architectural modeling, design automation, and debug
Strong debug and problem-solving skills, with the ability to root-cause complex issues across hardware and software boundaries
PhD degree in Computer Engineering, Electrical Engineering, or a related field
Experience in hardware/software co-design, including in mixed hardware/software datapaths, such as in the context of DSPs, GPUs, and ML accelerators
Knowledge of arithmetic units, processor design, accelerators, bus architectures, fabrics/NoC or memory hierarchies.
Knowledge of high performance and low power design techniques
Fluency and comfort with AI tools to accelerate and improve design and debug
Experience with Chisel (Scala) or other hardware DSLs for RTL generation

Nice-to-haves

None flagged.

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

pythonmlai

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