Job description

Description We are looking for a talented and experienced DFT Tech Lead. As a DFT Tech Lead you will work closely with all other design teams – backend, vlsi, verification and analog, fully responsible for defining, implementing, and deploying advanced design-for-test (DFT) methodologies for highly complex digital and mixed-signal chips. You will define silicon test strategies, DFT/DFD architecture, and create DFT and Debug specifications for complex next generation SoCs. Requirements Minimum qualifications: • 8+ Experience in DFT specification definition, architecture, insertion, and analysis in designs • Experience in silicon bring-up, debug, and validation of DFT features on ATE, debugging ATPG patterns, Compressed ATPG patterns, MBIST, and JTAG-related issues • Experience in fault modeling Preferred qualifications: • Master's degree in Electrical Engineering. • Experience in IP integration (memories, Test controllers, TAP, MBIST). • Experience using EDA Test tools like Design/Fusion Compiler, DFT Max, SpyGlass, Modus, Tessent, and TestKompress. • Experience and understanding of ASIC DFT, synthesis, simulation and verification flow. • Excellent attention to detail organizational, problem-solving, and communication skills. Responsibilities: • Create SoC DFT strategy and architecture (ATPG/DFT/MBIST) • Work on hierarchical design • Debug all Design Rule checks, apply design fixes to achieve high test quality • Insert all DFT logic - boundary scan, scan chains, DFT Compression, Logic BIST, TAP controller, Clock Control block, and other DFT IP blocks. • Insert and hook up MBIST logic. • Define test plan for special analog IPs and implement. • Document DFT architecture and test sequences, including boot-up sequence associated with test pins.

Requirements

Must-haves

We are looking for a talented and experienced DFT Tech Lead.
8+ Experience in DFT specification definition, architecture, insertion, and analysis in designs
Experience in silicon bring-up, debug, and validation of DFT features on ATE, debugging ATPG patterns, Compressed ATPG patterns, MBIST, and JTAG-related issues
Experience in fault modeling
Create SoC DFT strategy and architecture (ATPG/DFT/MBIST)
Work on hierarchical design
Debug all Design Rule checks, apply design fixes to achieve high test quality
Insert all DFT logic - boundary scan, scan chains, DFT Compression, Logic BIST, TAP controller, Clock Control block, and other DFT IP blocks.
Insert and hook up MBIST logic.
Define test plan for special analog IPs and implement.
Document DFT architecture and test sequences, including boot-up sequence associated with test pins.

Nice-to-haves

Master's degree in Electrical Engineering.
Experience in IP integration (memories, Test controllers, TAP, MBIST).
Experience using EDA Test tools like Design/Fusion Compiler, DFT Max, SpyGlass, Modus, Tessent, and TestKompress.
Experience and understanding of ASIC DFT, synthesis, simulation and verification flow.
Excellent attention to detail organizational, problem-solving, and communication skills.

Application prep

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Platform: comeet
Effort: medium