Job description

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: High Speed Interconnect Product (HSIP) Group Broadcom is a global leader and innovator in semiconductor solutions for wired and wireless communications. The High Speed Interconnect Product (HSIP) line of business produces the industry’s lowest power and highest performance (100Gbps to 400Gbps) highly integrated physical layer transceivers (PHYs) to meet the increasing demand in AI data center, enterprise network performance and server virtualization. We are looking for a bright, motivated, innovative, and hardworking recent graduate with MS degree, or BS with a minimum of 3 years of experience to join our top notch engineering team. Here you will utilize the technical skills you already learned at school and develop new skills in the verification of communication ASICs with leading edge technologies and tools. You will work closely with marketing, architecture, firmware, physical and layout teams on full product development cycle from definition to production. You will be challenged and gain valuable experience towards developing a successful career in ASIC. Job responsibilities include: • Develop thorough understanding of IEEE Ethernet protocols. • Understand chip architecture, microarchitecture and design specification. • Develop advanced verification environment and testbench components in SystemVerilog UVM. • Participate in block level and chip level verification tasks. • Infrastructure work including developing scripts and tools for efficiency and quality improvements. Job Requirements: • Bachelors in Engineering and 5 years of related experience, or recent grad with Masters or PhD degree in Engineering • Design/Verification experience, or equivalent experience. • Logic design, Electronic circuit design and related course work to provide a broad background in the area of ASIC design and verification. • Proficiency with HDL language such as Verilog, SystemVerilog or VHDL is a must. • Proficiency with C/C programming language and hands-on exposure to Object Oriented Programming is a big plus. • Proficiency with scripting in various languages such as Python, PERL, TCL is a big plus. • Self-motivated, good communicator, quick learner and good team player. • Display positive attitude and demonstrate flexibility in day-to-day work. Compensation and Benefits The annual base salary range for this position is USD 101,000.00 To USD 162,000.00 As a valued member of our team, you ll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company s growth. All subject to relevant plan documents and award agreements. Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence. Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law. If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Requirements

Must-haves

If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)
If you already have a Candidate Account, please Sign-In before you apply.
Develop thorough understanding of IEEE Ethernet protocols.
Understand chip architecture, microarchitecture and design specification.
Develop advanced verification environment and testbench components in SystemVerilog UVM.
Participate in block level and chip level verification tasks.
Infrastructure work including developing scripts and tools for efficiency and quality improvements.
Bachelors in Engineering and 5 years of related experience, or recent grad with Masters or PhD degree in Engineering
Design/Verification experience, or equivalent experience.
Logic design, Electronic circuit design and related course work to provide a broad background in the area of ASIC design and verification.
Proficiency with HDL language such as Verilog, SystemVerilog or VHDL is a must.
Proficiency with C/C programming language and hands-on exposure to Object Oriented Programming is a big plus.
Proficiency with scripting in various languages such as Python, PERL, TCL is a big plus.
Self-motivated, good communicator, quick learner and good team player.
Display positive attitude and demonstrate flexibility in day-to-day work.

Nice-to-haves

None flagged.

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

aipython

Platform: workday
Effort: long

Benefits

Benefits detected in the listing.

Dental

Vision

401(K)