Job description

Imagine a piloted air taxi that takes off vertically, then quietly carries you and your fellow passengers over the congested city streets below, enabling you to spend more time with the people and places that matter most. At Joby, we've been working to make that dream a reality since 2009 and we're now in the final stages of certifying our aircraft with the FAA. With plans to launch our aircraft in the US and Dubai, we're now scaling manufacturing and preparing for the launch of our commercial service. The successful candidate will play a crucial role in building and optimizing the dependable sensing and computing systems needed to bring the dream of Urban Air Mobility to market. They will contribute to a team that is focused on implementing signal processing and algorithm accelerators in a combination of hardware and software. The successful candidate will excel in a highly collaborative environment to design and modify processing systems that can be rigorously defined, designed, characterized, and verified, ensuring the safe operation of our aircraft. • Work with FPGA, hardware, motor control, software, data, safety, and systems engineers to understand current and future DSP and processing needs, constraints, and challenges. • Design new and optimize existing fault-tolerant FPGA-based DSP blocks for sensor acquisition, motor control, navigation, and hardware emulation applications. • Develop directed testbenches for DSP blocks based on bit-accurate reference models and assist FPGA verification engineers as needed for more formal verification. • Work in a rigorous aircraft certification-focused development environment and create the required models and documentation for the definition, validation, and verification of requirements as needed. • S./M.S./Ph.D. in relevant discipline (Electrical Engineering, Computer Science, Computer Engineering, Mechatronics, Physics, Mathematics, or similar field; or portfolio of designed and utilized FPGA/ASIC projects). • 5+ years’ experience in FPGA or ASIC design in VHDL, Verilog, or SystemVerilog. • Experience using MATLAB, Simulink, Python, or C for modeling signal processing systems. • Experience implementing fixed-point DSP blocks in RTL, such as IIR and FIR filters, PWM generators, delta-sigma modulators, PLLs, DFT/FFT processors, and CORDIC processors. • Familiarity with development in a Linux environment. Senior/Staff level will depend upon candidate qualifications, scope and abilities. • Experience with DO-254 FPGA compliance. • Experience with SEU mitigation for aviation or automotive applications. • Experience with C/C++ on embedded processing systems. • Experience with processor architecture and communications protocols, such as AXI, DMA, I2C, UART, SPI, SENT, and ethernet. • Experience with Xilinx FPGAs (Zynq, Artix) and Vivado toolchain experience, including creation of complex timing constraints. • Experience with model-based design and associated automated code generation tools. Compensation at Joby is a combination of base pay and Restricted Stock Units (RSUs). The target base pay for this position is $132,800 - $215,300. The compensation package will be determined by job-related knowledge, skills, and experience. Joby also offers a comprehensive benefits package, including paid time off, healthcare benefits, a 401(k) plan with a company match, an employee stock purchase plan (ESPP), short-term and long-term disability coverage, life insurance, and more. Joby is an Equal Opportunity Employer

Requirements

Must-haves

Work with FPGA, hardware, motor control, software, data, safety, and systems engineers to understand current and future DSP and processing needs, constraints, and challenges.
Design new and optimize existing fault-tolerant FPGA-based DSP blocks for sensor acquisition, motor control, navigation, and hardware emulation applications.
Develop directed testbenches for DSP blocks based on bit-accurate reference models and assist FPGA verification engineers as needed for more formal verification.
Work in a rigorous aircraft certification-focused development environment and create the required models and documentation for the definition, validation, and verification of requirements as needed.
S./M.S./Ph.D. in relevant discipline (Electrical Engineering, Computer Science, Computer Engineering, Mechatronics, Physics, Mathematics, or similar field; or portfolio of designed and utilized FPGA/ASIC projects).
5+ years’ experience in FPGA or ASIC design in VHDL, Verilog, or SystemVerilog.
Experience using MATLAB, Simulink, Python, or C for modeling signal processing systems.
Experience implementing fixed-point DSP blocks in RTL, such as IIR and FIR filters, PWM generators, delta-sigma modulators, PLLs, DFT/FFT processors, and CORDIC processors.
Familiarity with development in a Linux environment.
Senior/Staff level will depend upon candidate qualifications, scope and abilities.
Experience with DO-254 FPGA compliance.
Experience with SEU mitigation for aviation or automotive applications.
Experience with C/C++ on embedded processing systems.
Experience with processor architecture and communications protocols, such as AXI, DMA, I2C, UART, SPI, SENT, and ethernet.
Experience with Xilinx FPGAs (Zynq, Artix) and Vivado toolchain experience, including creation of complex timing constraints.
Experience with model-based design and associated automated code generation tools.
Joby is an Equal Opportunity Employer

Nice-to-haves

None flagged.

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

python

Platform: icims
Effort: medium

Benefits

Benefits detected in the listing.

401(K)

Paid Time Off