Job description

Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate, high-energy engineers to help achieve that mission. #azurehwjobs #SCHIE Responsibilities • Functional validation of PCIe IP at Block, Cluster or Fullchip using UVM/C test bench and Verification IP (VIP) • Develop Test Plan and write unit tests for functional validation • Create and Manage regression suites, debug failures, and drive timely resolution • Innovate to improve validation efficiency through methodologies and tools • Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion Qualifications Required Qualifications • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience. Other Qualifications Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. Preferred Qualifications • Experience with protocol verification for PCIe, especially Gen6/Gen7, and related standards such as NVMe or RDMA • Experience with Cluster, SoC, or Fullchip level verification • Prior verification experience with PCIe, both at the Transaction and Data Link Layer • Strong proficiency in Verilog, System Verilog, and UVM based testbench environment. • Good understanding of computer architecture and digital design fundamentals • Experience building UVM testbenches, managing regressions, meeting code coverage and functional coverage goals to succesfull tapeout. Silicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $142,800 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year. Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: careers.microsoft.com This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled. Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

Requirements

Must-haves

#azurehwjobs
Functional validation of PCIe IP at Block, Cluster or Fullchip using UVM/C test bench and Verification IP (VIP)
Develop Test Plan and write unit tests for functional validation
Create and Manage regression suites, debug failures, and drive timely resolution
Innovate to improve validation efficiency through methodologies and tools
Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion
Other Qualifications
This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.

Nice-to-haves

Experience with protocol verification for PCIe, especially Gen6/Gen7, and related standards such as NVMe or RDMA
Experience with Cluster, SoC, or Fullchip level verification
Prior verification experience with PCIe, both at the Transaction and Data Link Layer
Strong proficiency in Verilog, System Verilog, and UVM based testbench environment.
Good understanding of computer architecture and digital design fundamentals
Experience building UVM testbenches, managing regressions, meeting code coverage and functional coverage goals to succesfull tapeout.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:

Application prep

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