Job description

Reality Labs focuses on delivering Meta's vision through creating advanced AR/AI enabled wearables. The compute performance and power efficiency requirements of wearables require custom silicon. Reality Labs Silicon team is driving the state-of-the-art forward with breakthrough work in AI, augmented reality, computer vision, machine learning, graphics, displays, and sensors. Our chips will enable wearable devices where our real and virtual worlds will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistors, through architecture, firmware, and algorithms. As an SoC Architect, you will play a key role in driving top-level chip architecture that meets the power and size constraints of wearable devices. Define and drive SoC-level architecture for AR or AI wearable chips, including compute subsystems, memory hierarchy, interconnect topology, and power delivery strategies Lead architectural exploration and trade-off analysis across heterogeneous compute blocks, including CPU, GPU, vision, audio, and ML accelerators Collaborate with algorithms, firmware, and software teams to drive hardware-software co-design decisions Partner with IP vendors, power and performance architects, IP architects, and internal design teams to evaluate and integrate third-party and custom IP blocks into the SoC architecture Develop architectural specifications, interface definitions, and design guidelines that guide RTL implementation and physical design teams Provide architectural leadership and technical direction to other engineers across silicon, systems, and platform teams working on wearable device programs Contribute to long-term silicon roadmap planning by evaluating emerging process technologies, memory technologies, and compute paradigms relevant to AR/VR applications Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 8+ years of experience in SoC architecture, microarchitecture definition, or system-level hardware design for consumer electronics or mobile/wearable platforms Experience architecting heterogeneous SoCs, encompassing CPU, GPU, neural processing, and hardware accelerator subsystems Expertise with high-speed I/O interfaces such as PCIe, USB, and LPDDR Experience with memory subsystem architecture, including cache hierarchy design, DRAM interface optimization, and on-chip interconnect (NoC) design Experience collaborating across hardware, firmware, and software disciplines to drive hardware-software co-design for real-time or latency-constrained workloads Experience architecting silicon for AR, VR, or wearable devices with stringent power and thermal constraints Experience with AI/ML accelerator architecture and optimizing memory hierarchy for neural network workloads for on-device inference Familiarity with advanced process node design considerations (e.g., 5nm and below) and their implications for SoC architecture decisions Experience with system MMUs and hardware security

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Keywords to mirror

aimachine learningml

Platform: meta
Effort: medium

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Vision