Job description

NORMAL COMPUTING | BUILD WITH US Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, Silicon Valley (Mountain View), and London. THE ROLE As a Lead RTL Design Engineer at Normal, you will lead and own the design of the digital logic at the heart of Normal's thermodynamic hardware. This work sits at the intersection of classical ASIC design, novel computing architectures, and a development environment where the hardware and the algorithms are built together, not in sequence. You will lead and own RTL from microarchitecture to tapeout: writing microarchitecture specifications, creating synthesizable SystemVerilog, working with design verification engineers to fully test the design using conventional and formal methods, and working closely with physical design to make sure the design meets area and timing constraints. As a Lead, you will help with hiring, create and refine the design methodology, organize the design team around schedule and track progress. Because Normal's chips are not standard accelerators, the Lead RTL engineer here is closer to first-principles decisions than at a larger company. You will be shaping architecture, not just implementing it. This role requires a seasoned engineer with a track record of driving key initiatives, energizing the RTL team, and fostering cross-functional alignment across architecture, verification, and physical design. The ideal candidate has successfully led silicon through tapeout sign-off, played an active role in RTL implementation and design closure, and thrives in a dynamic setting where system specifications evolve alongside architectural and design development. WHAT YOU WILL OWN - Team Leadership: Organize and set the standard and high expectations for the RTL design team. Foster a collaborative and execution focused environment. - RTL Design: Create and enforce RTL coding standards. Write and own synthesizable RTL in SystemVerilog across blocks ranging from datapath logic to control and memory interfaces. - Microarchitecture: Work with architecture to translate high-level specifications into implementable microarchitectures. - Verification: Work closely with the verification team to review verification plans, assist on debug, and become a partner in closing coverage. - Physical Design Collaboration: Collaborate with physical design on timing closure, PPA optimization, floorplanning constraints, and DFT. - Design Reviews: Participate in design reviews and contribute to architecture decisions, not just implementation. - Tapeout & Bring-up: Support tapeout preparation, create tapeout criteria, signoff on tapeout readiness, and post-silicon bring-up as needed. - FPGA Prototyping: Own the FPGA prototyping flow for the team, from mapping the ASIC RTL onto the prototyping platform through timing closure and bring-up in Vivado, including vendor IP such as PCIe and memory controllers. WHAT MAKES YOU A GREAT FIT - Experience leading an RTL design team through multiple tapeouts. This includes block and toplevel work. - Hands-on experience writing production RTL in SystemVerilog and closing it through synthesis and place-and-route for multiple blocks and design. - Experience prototyping ASIC RTL on FPGAs (synthesis, place and route and timing closure in Vivado), with lab bring-up and debug. - Experience working on datapaths, pipelines, or custom logic where the microarchitecture was not fully specified upfront - Strong debugging instincts across simulation, waveforms, and formal counterexamples - Ability to work directly with architects and physical designers BONUS POINTS - Experience at an AI chip company where design and verification were tightly coupled - Experience with multiple interface architectures, for example PCIe, Ethernet, and memory devices. - Experience with AI-assisted RTL or EDA tooling in your design workflow - Exposure to physical design constraints, floorplanning, or timing-driven RTL development Equal Employment Opportunity Statement Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status. Accessibility Accommodations Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at accommodations@normalcomputing.com. Privacy Notice By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Applicant Privacy Notice normalcomputing.com.

Requirements

Must-haves

Team Leadership: Organize and set the standard and high expectations for the RTL design team. Foster a collaborative and execution focused environment.
RTL Design: Create and enforce RTL coding standards. Write and own synthesizable RTL in SystemVerilog across blocks ranging from datapath logic to control and memory interfaces.
Microarchitecture: Work with architecture to translate high-level specifications into implementable microarchitectures.
Verification: Work closely with the verification team to review verification plans, assist on debug, and become a partner in closing coverage.
Physical Design Collaboration: Collaborate with physical design on timing closure, PPA optimization, floorplanning constraints, and DFT.
Design Reviews: Participate in design reviews and contribute to architecture decisions, not just implementation.
Tapeout & Bring-up: Support tapeout preparation, create tapeout criteria, signoff on tapeout readiness, and post-silicon bring-up as needed.
Experience leading an RTL design team through multiple tapeouts. This includes block and toplevel work.
Hands-on experience writing production RTL in SystemVerilog and closing it through synthesis and place-and-route for multiple blocks and design.
Experience prototyping ASIC RTL on FPGAs (synthesis, place and route and timing closure in Vivado), with lab bring-up and debug.
Experience working on datapaths, pipelines, or custom logic where the microarchitecture was not fully specified upfront
Strong debugging instincts across simulation, waveforms, and formal counterexamples
Ability to work directly with architects and physical designers

Nice-to-haves

Experience at an AI chip company where design and verification were tightly coupled
Experience with multiple interface architectures, for example PCIe, Ethernet, and memory devices.
Experience with AI-assisted RTL or EDA tooling in your design workflow
Exposure to physical design constraints, floorplanning, or timing-driven RTL development

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

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