Job description

We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world! We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive. Our Purpose TERADYNE , where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supported to innovate and learn something new every day. We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team – one that makes better decisions, drives innovation and delivers better business results. Opportunity Overview Teradyne is seeking an experienced Physical Design Lead to join our Silicon Technology Engineering (STE) organization within the Digital ASIC Group. This team develops advanced-node, large-scale mixed-signal ASICs that are foundational to Teradyne’s next-generation SoC and memory test platforms. In this highly visible technical leadership role, you will own RTL-to-GDSII execution for complex ASICs, working closely with digital and analog designers, product architects, and chip leads. You will guide physical design architecture, mentor engineers, and play a critical role in delivering high-quality, first-pass silicon at advanced process nodes. What You’ll Do • Lead and mentor a team of physical design engineers across the full project lifecycle • Lead high-level physical design planning and define PD architecture in collaboration with chip and system architects • Develop and own chip floorplans, timing budgets, power estimates, and pin planning • Partner with design teams to develop high-quality SDC constraints • Drive RTL-to-netlist activities including synthesis, logical equivalence checking (LEC), clock domain crossing checks (CDC), and static timing analysis (STA) • Support hands-on place-and-route (P&R) for critical and high-speed blocks • Collaborate with a backend physical design house to support P&R execution, debug flow or implementation issues, and meet schedule and quality goals • Integrate complex IP such as PCIe, DDR5/DDR6, UFS, and SerDes • Ensure robust signoff closure including DRC/LVS and EM/IR analysis • Develop, enhance, and maintain physical design tool flows and automation All About You We seek individuals who share our passion and determination. Our commitment to customer success drives us to go the extra mile. If you’re ready to join us in this mission, take a closer look at the minimum criteria for the position. • 10+ years of hands-on ASIC physical design experience, including leadership of large or complex PD projects • Proven experience at advanced technology nodes (16nm and below) • Deep expertise in RTL-to-GDSII flows and timing closure • Strong understanding of STA, constraints development, and signoff methodologies • Experience integrating high-speed and complex IP (e.g., PCIe, DDR5/DDR6, UFS, SerDes) • Proficiency with industry-standard EDA tools (Cadence preferred) • Strong scripting and automation skills using Tcl, Python, and/or Make • Ability to lead technically, communicate clearly, and collaborate across disciplines • BS or MS in Electrical Engineering (or equivalent practical experience) Why Teradyne • Work on cutting-edge silicon that directly impacts the semiconductor ecosystem • High technical ownership and visibility • Collaborative, engineering-driven culture • Competitive compensation, benefits, and career growth opportunities We are an equal-opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform crucial job functions, and to receive other benefits and privileges of employment. Compensation: The base salary range for this role is $192,300 to $307,600. This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location. Incentive Plan: This job is eligible for discretionary bonus(es) based on financial performance. Benefits: Teradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more.  Please click here to see details.

Requirements

Must-haves

Opportunity Overview
What You’ll Do
Lead and mentor a team of physical design engineers across the full project lifecycle
Lead high-level physical design planning and define PD architecture in collaboration with chip and system architects
Develop and own chip floorplans, timing budgets, power estimates, and pin planning
Partner with design teams to develop high-quality SDC constraints
Drive RTL-to-netlist activities including synthesis, logical equivalence checking (LEC), clock domain crossing checks (CDC), and static timing analysis (STA)
Support hands-on place-and-route (P&R) for critical and high-speed blocks
Collaborate with a backend physical design house to support P&R execution, debug flow or implementation issues, and meet schedule and quality goals
Integrate complex IP such as PCIe, DDR5/DDR6, UFS, and SerDes
Ensure robust signoff closure including DRC/LVS and EM/IR analysis
Develop, enhance, and maintain physical design tool flows and automation
All About You
10+ years of hands-on ASIC physical design experience, including leadership of large or complex PD projects
Proven experience at advanced technology nodes (16nm and below)
Deep expertise in RTL-to-GDSII flows and timing closure
Strong understanding of STA, constraints development, and signoff methodologies
Experience integrating high-speed and complex IP (e.g., PCIe, DDR5/DDR6, UFS, SerDes)
Strong scripting and automation skills using Tcl, Python, and/or Make
Ability to lead technically, communicate clearly, and collaborate across disciplines
BS or MS in Electrical Engineering (or equivalent practical experience)
Why Teradyne

Nice-to-haves

Proficiency with industry-standard EDA tools (Cadence preferred)
Incentive Plan: This job is eligible for discretionary bonus(es) based on financial performance.

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

gopython

Platform: successfactors
Effort: medium

Benefits

Benefits detected in the listing.

Dental

Vision