Job description

Specify, design, and help in the verification and lab bring-up of advanced mixed-signal circuits (digital side) Knowledge of mixed signal concepts Knowledge of RTL design Knowledge of Verilog and SystemVerilog Knowledge of front-end tools (Verilog simulators, linters, clock-domain crossing checkers) Good communication and presentation skills Master´s degree or PhD in Electrical/Computer Engineering or proven industrial experience/degree equivalent Good knowledge of scripting languages. Perl and Python are plusses Good knowledge of synthesis, static timing, DFT, is a plus Good knowledge of SystemVerilog assertions, checkers, and other design verification techniques are a plus

Requirements

Must-haves

Specify, design, and help in the verification and lab bring-up of advanced mixed-signal circuits (digital side)
Knowledge of mixed signal concepts
Knowledge of RTL design
Knowledge of Verilog and SystemVerilog
Knowledge of front-end tools (Verilog simulators, linters, clock-domain crossing checkers)
Good communication and presentation skills
Master´s degree or PhD in Electrical/Computer Engineering or proven industrial experience/degree equivalent
Good knowledge of scripting languages. Perl and Python are plusses

Nice-to-haves

Good knowledge of synthesis, static timing, DFT, is a plus
Good knowledge of SystemVerilog assertions, checkers, and other design verification techniques are a plus

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

python

Platform: apple
Effort: medium