Job description

As a RTL Engineer, you will own or participate in the following: • Microarchitecture development and specification - from early high-level architectural exploration through micro architectural research and arriving at a detailed specification • RTL feature ownership – development, assessment and refinement of new RTL features to target power, performance, area and timing goals • Validation - support test bench development and simulation for functional and performance verification • Performance exploration and correlation - explore high performance strategies and validate that the RTL design meets targeted performance • Design delivery - work with multifunctional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability, and power Minimum BS and 20+ years of relevant industry experience Experience with microprocessor architecture Experience with Verilog or VHDL Knowledge of logic design principles Expertise with one or more of the following areas: instruction fetch and decode, branch prediction, instruction scheduling, register renaming, out-of-order execution, integer and floating point execution, load/store execution, or cache and memory subsystems Understanding of timing, power and area tradeoffs in CPU microarchitecture Understanding of low power and high performance microarchitecture techniques Experience using an interpretive language such as Perl or Python Experience with simulators and waveform debugging tools such as Verdi

Requirements

Must-haves

As a RTL Engineer, you will own or participate in the following:
Microarchitecture development and specification - from early high-level architectural exploration through micro architectural research and arriving at a detailed specification
RTL feature ownership – development, assessment and refinement of new RTL features to target power, performance, area and timing goals
Validation - support test bench development and simulation for functional and performance verification
Performance exploration and correlation - explore high performance strategies and validate that the RTL design meets targeted performance
Design delivery - work with multifunctional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability, and power
Minimum BS and 20+ years of relevant industry experience
Experience with microprocessor architecture
Experience with Verilog or VHDL
Knowledge of logic design principles
Understanding of timing, power and area tradeoffs in CPU microarchitecture
Understanding of low power and high performance microarchitecture techniques
Experience using an interpretive language such as Perl or Python
Experience with simulators and waveform debugging tools such as Verdi

Nice-to-haves

None flagged.

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

python

Platform: apple
Effort: medium