Job description

We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world! We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive. Our Purpose TERADYNE , where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supported to innovate and learn something new every day. We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team – one that makes better decisions, drives innovation and delivers better business results. Opportunity Overview Teradyne’s Semiconductor Test Division in Agoura Hills, CA is looking for an enthusiastic candidate for the position of Senior Analog Design Engineer, to design low high-speed circuits in mixed-signal ICs for ATE (Automatic Test Equipment) instruments. We are looking for a candidate with experience in FINFET, general CMOS, and BCD technologies. Responsibilities include: • Develop detailed circuit specifications for mixed signal circuits • Conceive circuit architectures and transistor level circuit topologies that satisfy required performance • Physical implementation (layout) of high speed circuits, either directly or assisting. • Optimization of circuits via simulation (with Cadence EDA tools) over all process and operating conditions • Integration of circuit elements into large analog/mixed signals ASICs • Participation in the characterization of ASIC circuits. All About You We seek individuals who share our passion and determination. Our commitment to customer success drives us to go the extra mile. If you’re ready to join us in this mission, take a closer look at the minimum criteria for the position. • MSEE with 5 years of experience or PhD in electrical engineering with 3 years experience in the design and characterization of multiple, high frequency and high scale of integration mixed signal integrated circuits • Thorough knowledge of high frequency, broad-band Analog Mixed-Signal IC design – both electrical and physical design • Desire experience in design of VCOs, PLLs, DLLs, ADCs, DACs, clock and data recovery, broadband amplifiers, bias generators, clock distribution networks, high frequency I/Os, high frequency CML designs, high voltage, power circuits • Solid understanding of CMOS semiconductor device physics and device modeling • Solid understanding of electromagnetic theory • Solid understanding of transmission line theory • Solid understanding of thermal effects of various circuit topologies and different package types • Involvement in all phases of multiple IC developments from specification to product introduction • Experience with Cadence Skill or Ocean scripting for automating test benches is a plus. • Proficiency in Verilog or Verilog-A modeling is highly desired. • Direct experience in FINFET desired • Generic experience in deep sub-micron CMOS (nodes We are an equal-opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform crucial job functions, and to receive other benefits and privileges of employment. Compensation: The base salary range for this role is $119,200 to $190,700. This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location. Incentive Plan: This job is eligible for discretionary bonus(es) based on financial performance. Benefits: Teradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more.  Please click here to see details.

Requirements

Must-haves

Opportunity Overview
Develop detailed circuit specifications for mixed signal circuits
Conceive circuit architectures and transistor level circuit topologies that satisfy required performance
Physical implementation (layout) of high speed circuits, either directly or assisting.
Optimization of circuits via simulation (with Cadence EDA tools) over all process and operating conditions
Integration of circuit elements into large analog/mixed signals ASICs
Participation in the characterization of ASIC circuits.
All About You
MSEE with 5 years of experience or PhD in electrical engineering with 3 years experience in the design and characterization of multiple, high frequency and high scale of integration mixed signal integrated circuits
Thorough knowledge of high frequency, broad-band Analog Mixed-Signal IC design – both electrical and physical design
Solid understanding of CMOS semiconductor device physics and device modeling
Solid understanding of electromagnetic theory
Solid understanding of transmission line theory
Solid understanding of thermal effects of various circuit topologies and different package types
Involvement in all phases of multiple IC developments from specification to product introduction
Proficiency in Verilog or Verilog-A modeling is highly desired.
Direct experience in FINFET desired
Generic experience in deep sub-micron CMOS (nodes

Nice-to-haves

Experience with Cadence Skill or Ocean scripting for automating test benches is a plus.

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

Platform: successfactors
Effort: medium

Benefits

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Dental

Vision