Job description

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by over $1 billion in total funding from leading investors including Altimeter Capital, ICONIQ, Kleiner Perkins, Lightspeed Venture Partners, Redpoint Ventures, and T. Rowe Price — and with over $1 billion in signed contracts across commercial and US government customers, we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space. The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today's and tomorrow's massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits. With multiple launches in 2027 and plans to scale to 100 satellites a year, we're Building Bigger — helping develop the solar system and build toward a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a high-growth Series D-funded company, we'd love for you to apply. The Role We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that power next-generation satellite and space systems. In this role, you will contribute to the full physical design flow—from synthesis to GDSII—working closely with architecture, RTL, verification, and packaging teams. You’ll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have contributed to developing cutting-edge SoCs that will fly in space.  Responsibilities Execute the complete physical design flow for complex SoC blocks and top-level integration, including synthesis, floorplanning, place & route, CTS, STA, and physical verification. Perform timing closure and optimization across multiple corners and modes using industry-standard tools. Collaborate with front-end, verification, and DFT teams to ensure clean handoff and predictable convergence. Work with external physical design service providers and internal leads to review deliverables, resolve issues, and ensure schedule alignment. Develop and maintain scripts and automation to improve flow efficiency and consistency. Support physical sign-off activities including DRC/LVS, IR drop, EM, and power analysis. Assist in chip-level integration, ECOs, and tapeout preparation. Contribute to methodology development, tool evaluation, and flow documentation. Support your product through production and spaceflight. Required Qualifications   Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field. 5–10 years of experience in ASIC physical design for complex SoCs. Hands-on experience with industry-standard tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus, or equivalent). Strong understanding of timing analysis, power optimization, and physical verification flows. Experience with hierarchical or flat SoC design methodologies. Familiarity with FinFET technologies. Working knowledge of DFT, UPF/CPF power intent, and ECO implementation. Strong problem-solving skills and ability to work cross-functionally in fast-paced environments. Preferred Qualifications   Exposure to radiation-hardened or space-qualified ASICs. Experience with chip-package co-design or advanced packaging (2.5D/3D). Familiarity with physical design service vendor management or offshore collaboration. Experience with sign-off through TSMC. Experience with Gate-All-Around technologies. Experience working in cross-functional, geographically distributed teams. Compensation and Benefits: Base salary range for this role is $170,000 – $250,000 + equity in the company Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks If you don’t meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged! If you need a reasonable accommodation as part of your application for employment or interviews with us, please let us know. Export Compliance As defined in the ITAR, “U.S. Persons” include U.S. citizens, lawful permanent residents (i.e., Green Card holders), and certain protected individuals (e.g., refugees/asylees, American Samoans). Please consult with a knowledgeable advisor if you are unsure whether you are a “U.S. Person.” The person hired for this role will have access to information and items controlled by U.S. export control regulations, including the export control regulations outlined in the International Traffic in Arms Regulation (ITAR). The person hired for this role must therefore either be a “U.S. person” as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license. Equal Opportunity K2 Space is an Equal Opportunity Employer; employment with K2 Space is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

Requirements

Must-haves

Execute the complete physical design flow for complex SoC blocks and top-level integration, including synthesis, floorplanning, place & route, CTS, STA, and physical verification.
Perform timing closure and optimization across multiple corners and modes using industry-standard tools.
Collaborate with front-end, verification, and DFT teams to ensure clean handoff and predictable convergence.
Work with external physical design service providers and internal leads to review deliverables, resolve issues, and ensure schedule alignment.
Develop and maintain scripts and automation to improve flow efficiency and consistency.
Support physical sign-off activities including DRC/LVS, IR drop, EM, and power analysis.
Assist in chip-level integration, ECOs, and tapeout preparation.
Contribute to methodology development, tool evaluation, and flow documentation.
Support your product through production and spaceflight.
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
5–10 years of experience in ASIC physical design for complex SoCs.
Hands-on experience with industry-standard tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus, or equivalent).
Strong understanding of timing analysis, power optimization, and physical verification flows.
Experience with hierarchical or flat SoC design methodologies.
Familiarity with FinFET technologies.
Working knowledge of DFT, UPF/CPF power intent, and ECO implementation.
Strong problem-solving skills and ability to work cross-functionally in fast-paced environments.

Nice-to-haves

Exposure to radiation-hardened or space-qualified ASICs.
Experience with chip-package co-design or advanced packaging (2.5D/3D).
Familiarity with physical design service vendor management or offshore collaboration.
Experience with sign-off through TSMC.
Experience with Gate-All-Around technologies.
Experience working in cross-functional, geographically distributed teams.

Application prep

Use the role’s language and application details while tailoring your materials.

Platform: greenhouse
Effort: quick

Benefits

Benefits detected in the listing.

Dental

Vision

Paid Time Off

Parental Leave