Job description

Overview Microsoft’s Silicon, Cloud Hardware, and Infrastructure Engineering ( SCHIE ) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are a Design Verification Engineer II to help achieve that mission. The Compute Silicon & Manufacturing Engineering ( CSME ) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantages to Microsoft and enable our customers to achieve more. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Verification & Validation ( Verif&Val ) team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for a Design Verification Engineer II for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for a Design Verification Engineer II to join the team. Responsibilities The candidate for this position will be expected and able to complete the following responsibilities: • Own verification of one or more aspects/features of a custom IP/block or IP subsystem integration. • Learn about the design and interact with partner teams to define verification strategies and test plans. • Develop UVM-based or Formal verification environments and run and debug simulations to drive quality. • Apply random-stimulus and coverage-based techniques to find bugs and meet test plan goals. • Innovate to improve verification efficiency through methodologies or tools. • Apply industry leading generative AI solutions to verification work. • Coach and mentor others in your areas of expertise. • Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion. Qualifications Required Qualifications: • Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 2+ years technical engineering experience OR equivalent experience. Other Requirements: • Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. • This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations.  As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. Preferred Qualifications: • 2+ years of pre-silicon subsystem or IP/block level verification experience. • Demonstrated understanding of one or more of the following: fabric interconnects, coherency, Coherent Hub Interface (CHI), Advanced eXtensible Interface (AXI), Advanced Microcontroller Bus Architecture (AMBA), virtualization, security, interrupts, PCIe, CXL, protocol bridges or other complex IP/blocks or subsystems. • Understanding of IP verification from definition to silicon, including writing IP/block or subsystem level test plans, developing tests, debugging failures and coverage signoff. • Experience creating, maintaining, or integrating test benches, checkers and stimulus using Universal Verification Methodology (UVM), System Verilog Test Bench (SVTB), and optionally Python based post-processing checking. • Aptitude for writing scripts/software with industry standard languages like Python. • Experience applying generative AI to day-to-day tasks. #SCHIE #CSME Silicon Engineering IC3 - The typical base pay range for this role across the U.S. is USD $102,100 - $202,200 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $133,800 - $219,200 per year. Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: careers.microsoft.com This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled. Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

Requirements

Must-haves

We are looking for a Design Verification Engineer II to join the team.
The candidate for this position will be expected and able to complete the following responsibilities:
Own verification of one or more aspects/features of a custom IP/block or IP subsystem integration.
Learn about the design and interact with partner teams to define verification strategies and test plans.
Develop UVM-based or Formal verification environments and run and debug simulations to drive quality.
Apply random-stimulus and coverage-based techniques to find bugs and meet test plan goals.
Innovate to improve verification efficiency through methodologies or tools.
Apply industry leading generative AI solutions to verification work.
Coach and mentor others in your areas of expertise.
Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion.
2+ years of pre-silicon subsystem or IP/block level verification experience.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.

Nice-to-haves

Understanding of IP verification from definition to silicon, including writing IP/block or subsystem level test plans, developing tests, debugging failures and coverage signoff.
Experience creating, maintaining, or integrating test benches, checkers and stimulus using Universal Verification Methodology (UVM), System Verilog Test Bench (SVTB), and optionally Python based post-processing checking.
Aptitude for writing scripts/software with industry standard languages like Python.
Experience applying generative AI to day-to-day tasks.

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

azureaipython

Platform: eightfold
Effort: medium

Benefits

Benefits detected in the listing.

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