Job description

Our Mission At Palo Alto Networks®, we’re united by a shared mission—to protect our digital way of life. We thrive at the intersection of innovation and impact, solving real-world problems with cutting-edge technology and bold thinking. Here, everyone has a voice, and every idea counts. If you’re ready to do the most meaningful work of your career alongside people who are just as passionate as you are, you’re in the right place. Who We Are In order to be the cybersecurity partner of choice, we must trailblaze the path and shape the future of our industry. This is something our employees work at each day and is defined by our values: Disruption, Collaboration, Execution, Integrity, and Inclusion. We weave AI into the fabric of everything we do and use it to augment the impact every individual can have. If you are passionate about solving real-world problems and ideating beside the best and the brightest, we invite you to join us! We believe collaboration thrives in person. That’s why most of our teams work from the office full time, with flexibility when it’s needed. This model supports real-time problem-solving, stronger relationships, and the kind of precision that drives great outcomes. Job Summary About the Role Join our ASIC team and help deliver the digital logic that powers our next-generation firewall platforms. You will own module design from specification through silicon bring-up, working with world-class verification and physical-design engineers to hit aggressive performance, power, and schedule goals. What You’ll Do Write clear design and micro-architecture specifications. Design SystemVerilog RTL that meets area, performance, and power targets. Verify your blocks with simulation, emulation, formal methods, and silicon bring-up. Collaborate with verification engineers to debug complex scenarios, close coverage, and add design-for-debug features. Partner with physical-design teams: review synthesis/timing reports, rewrite RTL to close critical paths, and consult on floor-planning for congestion/routability. Innovate : pilot AI-driven design or verification flows that cut schedule risk. Qualifications Required Qualifications BS in EE, CE, or CS (MSEE or equivalent military experience preferred). 10 years front-end ASIC design ownership, shipping 2 chips to mass production. Expert SystemVerilog RTL skills. Proven track record of selecting, integrating, and configuring complex IP blocks for high-speed interfaces such as PCIe, Ethernet, or DDR. Scripting proficiency (Python, C/C , Perl, bash or tcsh). Demonstrated strength in: Defining micro-architecture from high-level requirements. Datapath design expertise for intricate synch/asynch digital logic. Debugging across simulation, emulation, and silicon. Analyzing timing, power, and area reports and driving fixes. Excellent leadership, collaboration, and written/verbal communication. Preferred / Nice-to-Have Networking or cybersecurity domain knowledge. Experience with search-algorithm accelerators. Formal-verification ownership. Hands-on silicon validation and lab bring-up. Compensation Disclosure The compensation offered for this position will depend on qualifications, experience, and work location. For candidates who receive an offer at the posted level, the starting base salary (for non-sales roles) or base salary commission target (for sales/com-missioned roles) is expected to be the annual range listed below. The offered compensation may also include restricted stock units and a bonus. A description of our employee benefits may be found here . $156,400.00 - $253,000.00/yr Our Commitment We’re trailblazers that dream big, take risks, and challenge cybersecurity’s status quo. It’s simple: we can’t accomplish our mission without diverse teams innovating, together. We are committed to providing reasonable accommodations for all qualified individuals with a disability. If you require assistance or accommodation due to a disability or special need, please contact us at accommodations paloaltonetworks.com . Palo Alto Networks is an equal opportunity employer. We celebrate diversity in our workplace, and all qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or other legally protected characteristics. All your information will be kept confidential according to EEO guidelines. Is role eligible for Immigration Sponsorship?: Yes

Requirements

Must-haves

What You’ll Do Write clear design and micro-architecture specifications.
Design SystemVerilog RTL that meets area, performance, and power targets.
Verify your blocks with simulation, emulation, formal methods, and silicon bring-up.
Collaborate with verification engineers to debug complex scenarios, close coverage, and add design-for-debug features.
Partner with physical-design teams: review synthesis/timing reports, rewrite RTL to close critical paths, and consult on floor-planning for congestion/routability.
Innovate : pilot AI-driven design or verification flows that cut schedule risk.
10 years front-end ASIC design ownership, shipping 2 chips to mass production.
Expert SystemVerilog RTL skills.
Proven track record of selecting, integrating, and configuring complex IP blocks for high-speed interfaces such as PCIe, Ethernet, or DDR.
Scripting proficiency (Python, C/C , Perl, bash or tcsh).
Demonstrated strength in: Defining micro-architecture from high-level requirements.
Datapath design expertise for intricate synch/asynch digital logic.
Debugging across simulation, emulation, and silicon.
Analyzing timing, power, and area reports and driving fixes.
Excellent leadership, collaboration, and written/verbal communication.
Experience with search-algorithm accelerators.
Formal-verification ownership.
Hands-on silicon validation and lab bring-up.
Compensation Disclosure
$156,400.00 - $253,000.00/yr
Our Commitment
We’re trailblazers that dream big, take risks, and challenge cybersecurity’s status quo. It’s simple: we can’t accomplish our mission without diverse teams innovating, together.

Nice-to-haves

Required Qualifications BS in EE, CE, or CS (MSEE or equivalent military experience preferred).
Preferred / Nice-to-Have Networking or cybersecurity domain knowledge.

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

aipython

Platform: workday
Effort: long