Job description

Job Title: VLSI Verification Engineer Location: Santa Clara, CA Duration 6 Month Contract Job description: Verification engineers – OVM/UVM is Mandatory CPU subsystem/DDR/Modem verification All your information will be kept confidential according t o EEO guidelines.

Requirements

Must-haves

Job Title: VLSI Verification Engineer
Location: Santa Clara, CA
Duration 6 Month Contract
Verification engineers – OVM/UVM is Mandatory
CPU subsystem/DDR/Modem verification
All your information will be kept confidential according t o EEO guidelines.

Nice-to-haves

None flagged.

Application prep

Use the role’s language and application details while tailoring your materials.

Platform: smartrecruiters
Effort: medium