ASIC Design Engineer - Cache Controller

• Design and develop hardware for cache subsystem in high performance system on a chip (SoC).
• Develop cache micro-architecture based on architecture guidelines and model analysis.
• Explore architecture trade-offs in system performance, area, and power consumption.
• Develop and debug register-transfer level (RTL) design of various sections in the cache subsystem.
• Work on front-end netlist and area/timing analysis of the cache subsystem.
• Work with physical design team on the timing closure of the cache subsystem.
• In-depth knowledge of memory subsystem
• Academic experience with RTL/micro-architecture development
• Good understanding of PPA (performance/power/area) tradeoffs
• B.S. in a relevant field + 0 years of industry experience
• Cache design background including good understanding of different memory organizations and tradeoffs
• Experience with multi-processor cache coherence protocols
• Knowledge of high-performance coherent memory systems or interconnect architectures
• Knowledge of high-performance DRAM controller
• M.S in a relevant field.

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