Job description

As an CPU Technology Feasibility Implementation Engineer, you will be working on technology evaluation in the early design phase. You will be responsible for conducting experiments and analysis on process technology in CPU physical design and find out how to maximize PPA benefit from technology. Responsibilities include, but are not limited to: • Understanding new process technology and PPA trends • Driving RTL-to-GDS flow through synthesis/place-and-route for technology evaluation experiments • Analyzing PD results and identifying areas for improvements to maximize PPA benefit by new processes in all scopes such as technology, library/memory design, PD tools/methodology, RTL, etc. • Working with multi-functional engineering teams to resolve technology-related issues or improve PPA further • Performing and analyzing various PD experiments with new process technology to understand how to achieve high targets for performance, power, and area Minimum BS and 10+ years of relevant industry experience Experience with synthesis, PnR and clock flow, and PPA optimizations The ideal candidate will have implementation experience on high-performance CPU designs Deep understanding of process technology and its evaluation Deep understanding of power, performance, and area tradeoffs Deep knowledge of CPU microarchitecture including common critical loops for timing and understanding of low power microarchitecture and implementation techniques for CPUs Understanding of static timing and critical path closure techniques

Requirements

Must-haves

Understanding new process technology and PPA trends
Driving RTL-to-GDS flow through synthesis/place-and-route for technology evaluation experiments
Analyzing PD results and identifying areas for improvements to maximize PPA benefit by new processes in all scopes such as technology, library/memory design, PD tools/methodology, RTL, etc.
Working with multi-functional engineering teams to resolve technology-related issues or improve PPA further
Performing and analyzing various PD experiments with new process technology to understand how to achieve high targets for performance, power, and area
Minimum BS and 10+ years of relevant industry experience
Experience with synthesis, PnR and clock flow, and PPA optimizations
The ideal candidate will have implementation experience on high-performance CPU designs
Deep understanding of process technology and its evaluation
Deep understanding of power, performance, and area tradeoffs
Deep knowledge of CPU microarchitecture including common critical loops for timing and understanding of low power microarchitecture and implementation techniques for CPUs
Understanding of static timing and critical path closure techniques

Nice-to-haves

None flagged.

Application prep

Use the role’s language and application details while tailoring your materials.

Platform: apple
Effort: medium