Job description

Job Details: Job Description: About Altera At Altera™, our independence as the world’s largest pure ‑ play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry ‑ leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry. Position Overview Altera is a leader in FPGA innovation, delivering programmable solutions that power AI, cloud computing, networking, and edge applications. Our compiler and tools teams are central to enabling customers to efficiently map complex designs onto advanced FPGA architectures. Altera is seeking a FPGA Compiler Engineer (Placer) to join our Compiler team in San Jose, CA. This role focuses on developing and optimizing FPGA placement algorithms within the compiler toolchain, directly impacting performance, power efficiency, and overall design quality. The ideal candidate brings strong expertise in EDA algorithms, large-scale system optimization, and FPGA/ASIC physical design flows, along with a passion for solving complex, performance-critical problems. Key Responsibilities: Placement Algorithm Development: Design, implement, and enhance FPGA placement algorithms to optimize timing, congestion, and resource utilization. Compiler Flow Enhancement: Contribute to the end-to-end FPGA compilation flow, working closely with routing, synthesis, and timing teams. Performance Optimization: Improve runtime performance, scalability, and quality of results (QoR) for large and complex customer designs. Timing-Driven Placement: Develop and refine timing-aware placement strategies to support high-frequency, performance-critical designs. Cross-Functional Collaboration: Partner with architecture, routing, and STA teams to align placement strategies with FPGA device capabilities and constraints. Debug & Analysis: Analyze placement quality, congestion hotspots, and timing bottlenecks; drive improvements to convergence and design closure. Toolchain Integration: Integrate new placement capabilities into the compiler infrastructure and validate across diverse workloads. Why Join Altera? Work on core compiler technology that directly impacts FPGA performance and usability Solve challenging algorithmic problems at scale Collaborate with world-class teams across architecture, silicon, and software Salary The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings , etc. We also offer incentive opportunities that reward employees based on individual and company performance. $149.1 K - $215 .9K USD We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations . #CG-1 Qualifications: Minimum Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field. 6 years of experience in FPGA/ASIC CAD, EDA tools, or related fields. Experience in algorithms and data structures (optimization, graph theory, heuristics) Experience with placement algorithms or physical design flows Experience in C/C and software engineering best practices Experience with placement techniques (analytical placement, simulated annealing, partitioning, clustering) Experience with Timing-driven and congestion-driven optimization Experience in ASIC or FPGA physical design methodologies Experience in solving complex, large-scale optimization problems with high performance and scalability requirements. Preferred Qualifications Experience with FPGA toolchains (e.g., Quartus, Vivado ) Knowledge of FPGA architectures and interconnect fabrics Familiarity with routing and timing closure techniques Experience with parallel or distributed algorithms for EDA tools Scripting experience (e.g., Python, Tcl ) for tooling and automation Job Type: Regular Shift: Shift 1 (United States of America) Primary Location: San Jose, California, United States Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Requirements

Must-haves

Job Description: About Altera
Position Overview
The ideal candidate brings strong expertise in EDA algorithms, large-scale system optimization, and FPGA/ASIC physical design flows, along with a passion for solving complex, performance-critical problems.
Design, implement, and enhance FPGA placement algorithms to optimize timing, congestion, and resource utilization.
Contribute to the end-to-end FPGA compilation flow, working closely with routing, synthesis, and timing teams.
Improve runtime performance, scalability, and quality of results (QoR) for large and complex customer designs.
Develop and refine timing-aware placement strategies to support high-frequency, performance-critical designs.
Partner with architecture, routing, and STA teams to align placement strategies with FPGA device capabilities and constraints.
Analyze placement quality, congestion hotspots, and timing bottlenecks; drive improvements to convergence and design closure.
Integrate new placement capabilities into the compiler infrastructure and validate across diverse workloads.
Why Join Altera?
Work on core compiler technology that directly impacts FPGA performance and usability
Solve challenging algorithmic problems at scale
Collaborate with world-class teams across architecture, silicon, and software
We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations .
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.

Nice-to-haves

Experience with FPGA toolchains (e.g., Quartus, Vivado )
Knowledge of FPGA architectures and interconnect fabrics
Familiarity with routing and timing closure techniques
Experience with parallel or distributed algorithms for EDA tools
Scripting experience (e.g., Python, Tcl ) for tooling and automation
Job Type: Regular
Shift: Shift 1 (United States of America)
Primary Location: San Jose, California, United States

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aipython

Platform: workday
Effort: long