Job description

Our Mission At Palo Alto Networks®, we’re united by a shared mission—to protect our digital way of life. We thrive at the intersection of innovation and impact, solving real-world problems with cutting-edge technology and bold thinking. Here, everyone has a voice, and every idea counts. If you’re ready to do the most meaningful work of your career alongside people who are just as passionate as you are, you’re in the right place. Who We Are In order to be the cybersecurity partner of choice, we must trailblaze the path and shape the future of our industry. This is something our employees work at each day and is defined by our values: Disruption, Collaboration, Execution, Integrity, and Inclusion. We weave AI into the fabric of everything we do and use it to augment the impact every individual can have. If you are passionate about solving real-world problems and ideating beside the best and the brightest, we invite you to join us! We believe collaboration thrives in person. That’s why most of our teams work from the office full time, with flexibility when it’s needed. This model supports real-time problem-solving, stronger relationships, and the kind of precision that drives great outcomes. Job Summary Your Career As a Senior/Lead ASIC Emulation Engineer on the ASIC team, you will drive the execution, verification, and validation of high-complexity network security processors and compute architectures on state-of-the-art emulation and FPGA prototyping platforms. In this role, you will bridge the gap between pre-silicon hardware design, firmware/software development, and post-silicon validation. You will define emulation architecture, build scalable hybrid co-emulation environments, accelerate pre-silicon software bring-up, and ensure our next-generation firewall products achieve industry-leading performance and reliability. We expect office-based employees to be in the office four days per week, with one day working from where they choose. We believe being together facilitates casual conversations and those magic moments where we can work on issues and ideas informally. These moments build capability and deepen trusted relationships and allow our people to feel safe in taking risks and being disruptive. Your Impact Architect, bring up, and maintain enterprise-scale hardware emulation platforms (e.g., Palladium, ZeBu, Veloce) and hybrid co-emulation/virtual prototyping systems. Collaborate closely with ASIC Architecture, Design, Verification, and Software/Firmware teams to define pre-silicon emulation plans and execution timelines. Compile, synthesize, and fit multi-million/billion-gate SoC designs onto emulation hardware, performing power, timing, and capacity optimization. Develop and maintain transactors, rate adapters, speed adapters, and hybrid virtual interfaces (C/C , SystemC, DPI) to connect emulation models with host software testbenches and real-world network traffic generators. Enable pre-silicon software development and OS/driver bring-up by executing real-world workloads, benchmarks, and regression suites on the emulator. Debug complex, deep-trace hardware, firmware, and protocol-level failures using advanced emulation debug features (waveform captures, readback, dynamic probes, assertions). Automate build, deployment, triage, and regression flows using Python, Tcl, and CI/CD pipelines to optimize model compile speed and platform utilization. Partner with post-silicon validation teams to reproduce and triage silicon anomalies on the emulation platform. Qualifications Required Experience & Technical Skills Education: BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience. Core Experience: 8 years of hands-on experience in hardware emulation, FPGA prototyping, and ASIC verification, with a proven track record of shipping complex SoCs to production. Emulation Platforms: Expertise with at least one major emulation platform (Cadence Palladium, Synopsys ZeBu, or Siemens Veloce). Design & Verification Languages: Strong mastery of SystemVerilog, Verilog, C/C , and UVM/DPI interfaces. Platform & Debug Tools: Proficiency with platform debug tools (SimVision, Indago, Verdi, waveform probes, and dynamic memory readback). Speed Adapters & Transactors: Experience developing or integrating transactors, speed adapters, and virtual/physical interfaces (e.g., PCIe, Ethernet, DDR, CXL). Automation & Scripting: Advanced scripting skills in Python, Tcl, Perl, and UNIX shell to automate compilation, regression, and build infrastructure. Preferred Qualifications Experience with network hardware security architectures, high-speed Ethernet protocols (10G/100G/400G), or packet-processing pipelines. Familiarity with Hybrid Emulation / Virtual Platforms (SystemC, TLM2.0, QEMU integration). Background in C/C driver code development, OS kernel boot processes, or firmware debug on pre-silicon platforms. Knowledge of pre-silicon power estimation and thermal analysis tools on emulation platforms (e.g., Joules, PowerArtist, Palladium Power Analysis). Strong cross-functional leadership, vendor management skills, and clear communication abilities. Compensation Disclosure The compensation offered for this position will depend on qualifications, experience, and work location. For candidates who receive an offer at the posted level, the starting base salary (for non-sales roles) or base salary commission target (for sales/com-missioned roles) is expected to be the annual range listed below. The offered compensation may also include restricted stock units and a bonus. A description of our employee benefits may be found here . - /yr Our Commitment We’re trailblazers that dream big, take risks, and challenge cybersecurity’s status quo. It’s simple: we can’t accomplish our mission without diverse teams innovating, together. We are committed to providing reasonable accommodations for all qualified individuals with a disability. If you require assistance or accommodation due to a disability or special need, please contact us at accommodations paloaltonetworks.com . Palo Alto Networks is an equal opportunity employer. We celebrate diversity in our workplace, and all qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or other legally protected characteristics. All your information will be kept confidential according to EEO guidelines. Is role eligible for Immigration Sponsorship?: Yes

Requirements

Must-haves

Your Impact Architect, bring up, and maintain enterprise-scale hardware emulation platforms (e.g., Palladium, ZeBu, Veloce) and hybrid co-emulation/virtual prototyping systems.
Collaborate closely with ASIC Architecture, Design, Verification, and Software/Firmware teams to define pre-silicon emulation plans and execution timelines.
Compile, synthesize, and fit multi-million/billion-gate SoC designs onto emulation hardware, performing power, timing, and capacity optimization.
Develop and maintain transactors, rate adapters, speed adapters, and hybrid virtual interfaces (C/C , SystemC, DPI) to connect emulation models with host software testbenches and real-world network traffic generators.
Enable pre-silicon software development and OS/driver bring-up by executing real-world workloads, benchmarks, and regression suites on the emulator.
Debug complex, deep-trace hardware, firmware, and protocol-level failures using advanced emulation debug features (waveform captures, readback, dynamic probes, assertions).
Automate build, deployment, triage, and regression flows using Python, Tcl, and CI/CD pipelines to optimize model compile speed and platform utilization.
Partner with post-silicon validation teams to reproduce and triage silicon anomalies on the emulation platform.
Required Experience & Technical Skills Education: BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
Core Experience: 8 years of hands-on experience in hardware emulation, FPGA prototyping, and ASIC verification, with a proven track record of shipping complex SoCs to production.
Emulation Platforms: Expertise with at least one major emulation platform (Cadence Palladium, Synopsys ZeBu, or Siemens Veloce).
Design & Verification Languages: Strong mastery of SystemVerilog, Verilog, C/C , and UVM/DPI interfaces.
Platform & Debug Tools: Proficiency with platform debug tools (SimVision, Indago, Verdi, waveform probes, and dynamic memory readback).
Speed Adapters & Transactors: Experience developing or integrating transactors, speed adapters, and virtual/physical interfaces (e.g., PCIe, Ethernet, DDR, CXL).
Automation & Scripting: Advanced scripting skills in Python, Tcl, Perl, and UNIX shell to automate compilation, regression, and build infrastructure.
Familiarity with Hybrid Emulation / Virtual Platforms (SystemC, TLM2.0, QEMU integration).
Background in C/C driver code development, OS kernel boot processes, or firmware debug on pre-silicon platforms.
Knowledge of pre-silicon power estimation and thermal analysis tools on emulation platforms (e.g., Joules, PowerArtist, Palladium Power Analysis).
Strong cross-functional leadership, vendor management skills, and clear communication abilities.
Compensation Disclosure
Our Commitment
We’re trailblazers that dream big, take risks, and challenge cybersecurity’s status quo. It’s simple: we can’t accomplish our mission without diverse teams innovating, together.
All your information will be kept confidential according to EEO guidelines.

Nice-to-haves

Preferred Qualifications Experience with network hardware security architectures, high-speed Ethernet protocols (10G/100G/400G), or packet-processing pipelines.

Application prep

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Keywords to mirror

aipythonci/cd

Platform: workday
Effort: long

Benefits

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