Job description

Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for engineers to help achieve that mission. The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantages to Microsoft and enable our customers to achieve more. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Silicon Manufacturing and Product Engineering (SMPE) team is instrumental in defining and elivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for a Debug Engineer to join the team to support our mission as a key role with Maia & Cobalt silicon programs. #SCHIE #CSME #SMPE Responsibilities The candidate for this position will be expected and able to complete the following responsibilities: • This is a Hands-on role that responsible for execution on silicon debug, FA/FI and debug tool readiness   • The candidate should have experience silicon debug, design collateral procurement, readiness for physical/electrical debug tools and physical FA readiness   • The position requires someone with experience in semiconductor debug, fault isolation, failure analysis and product engineering yield debug  • The candidate will be responsible for developing new silicon debug methodologies for all test content types in our MFG flow   • The candidate will also be involved in root-cause of key product issues, circuit marginalities, special circuit failures and translate them into corrective actions in the design, our design methodologies and/or the MFG test flow    • Successful candidates have deep understanding and experience debugging product issues on ATE and using analytical equipment to isolate failures   • Deep understanding of best-in class silicon debug tools and methodologies is a must   • Successful candidates should have strong project leadership skills to manage external vendors, drive cross functional teams and drive sub-project as part of larger development programs  Qualifications Required Qualifications: • Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience • OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 2+ years technical engineering experience • OR equivalent experience. Preferred Qualifications: • 3+ years of experience in Developing Integrated Circuits (pre-silicon, first silicon bring-up, new product introduction). • 3+ years of experience in product and test engineering, specialize in ATE Test or silicon debug or FA/FI   • 3+ years of experience building debug methodology solutions for complex state-of-the-art SoC in advance process nodes • Experience with System-level debug and correlation to ATE   • Presentation and communication skills.  • Probability & statistics background including DOE’s.  • Knowledgeable in DFT and DFM techniques.  • Understanding of bring-up/debug, characterization/manufacturing test (on ATEs).  • Device physics background.  Screening Requirements • Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. • This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations.  As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. Silicon Engineering IC3 - The typical base pay range for this role across the U.S. is USD $102,100 - $202,200 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $133,800 - $219,200 per year. Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: careers.microsoft.com This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled. Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

Requirements

Must-haves

We are looking for a Debug Engineer to join the team to support our mission as a key role with Maia & Cobalt silicon programs.
The candidate for this position will be expected and able to complete the following responsibilities:
This is a Hands-on role that responsible for execution on silicon debug, FA/FI and debug tool readiness
The candidate should have experience silicon debug, design collateral procurement, readiness for physical/electrical debug tools and physical FA readiness
The position requires someone with experience in semiconductor debug, fault isolation, failure analysis and product engineering yield debug
The candidate will be responsible for developing new silicon debug methodologies for all test content types in our MFG flow
Successful candidates have deep understanding and experience debugging product issues on ATE and using analytical equipment to isolate failures
Deep understanding of best-in class silicon debug tools and methodologies is a must
Successful candidates should have strong project leadership skills to manage external vendors, drive cross functional teams and drive sub-project as part of larger development programs
OR equivalent experience.
3+ years of experience in Developing Integrated Circuits (pre-silicon, first silicon bring-up, new product introduction).
3+ years of experience in product and test engineering, specialize in ATE Test or silicon debug or FA/FI
3+ years of experience building debug methodology solutions for complex state-of-the-art SoC in advance process nodes
This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.

Nice-to-haves

Experience with System-level debug and correlation to ATE
Presentation and communication skills.
Probability & statistics background including DOE’s.
Knowledgeable in DFT and DFM techniques.
Understanding of bring-up/debug, characterization/manufacturing test (on ATEs).
Device physics background.
Screening Requirements
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:

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Platform: eightfold
Effort: medium

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