Job description

Sr. ASIC Design Engineer This role has been designed as 'Hybrid' with a requirement that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE. Job Description: Job Family Definition: HPE Networking is a leading provider of advanced routers and switches for the internet. We keep the world connected with speed, reliability, security, and ease of use. At HPE Networking Silicon group, we push the boundaries of what is possible in a piece of silicon die. We build cutting edge networking chips used to build our world-class routers and switches. Bring your passion and there are no boundaries to what you can accomplish here. We are like a start-up in a big company. Year after year, our group builds the most powerful and highest density networking chips. As part of our fast-paced silicon group, you will become an expert in building high-speed ASICs, from specifications to final netlist. We give you opportunities to work on complex modules and subsystems where you can challenge yourself and grow. Open communications, empowerment, innovation, teamwork, and customer success are the foundations of team culture. Thus, you set your own limits for learning, achievements, and rewards. Responsibilities: You will start with a functional specification of a module and produce a detailed micro-architecture specification that meets the power/area requirements. You will implement the design using Verilog or System Verilog Write functional coverage/SVA to help verification catch corner case bugs. You will work with the Physical Design team for optimal floorplan and timing closure. You will identify and fix timing in RTL to meet the frequency target. Work with the Verification team to make sure your block is fully validated. You will have opportunities to improve leadership skills by providing mentoring/guidance to new college-grad engineers and interns. Recommended skills Bachelor’s degree in Electrical Engineering required (Master’s strongly desired) with 5 years of relevant experience. Strong analytical/problem solving skills. Knowledge of Computer Architecture/networking protocols through graduate level courses or prior work is a plus. Strong coding skills in Verilog/System Verilog through courses/projects and previous work experience is desired. Knowledge of synthesis/lint and other state-of-the-art EDA tools is desired. Excellent written and verbal communications skills are good to have. Knowledge of Perl/Python is a plus. Experience with AI agentic tools is a plus. Accessibility HPE is committed to creating an inclusive and accessible workplace and encourages applications from all qualified individuals, including those with disabilities. If you believe you require accommodation during any stage of the application or interview process, please submit your request by completing our secure form linked here . Note: This option is reserved for applicants needing assistance/reasonable accommodation related to a disability. What We Can Offer You: Health & Wellbeing We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing. Personal & Professional Development We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have — whether you want to become a knowledge expert in your field or apply your skills to another division. Unconditional Inclusion We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. Let s Stay Connected: Follow HPECareers on Instagram to see the latest on people, culture and tech at HPE. Job: Engineering Job Level: TCP_04 "The expected salary/wage range for this position is provided below. Actual offer may vary from this range based upon geographic location, work experience, education/training, and/or skill level. – United States of America: Annual Salary USD 158,500 - 321,000 in California The listed salary range reflects base salary. Variable incentives may also be offered." Information about employee benefits offered in the US can be found at myhperewards.com HPE is an Equal Employment Opportunity/ Veterans/Disabled/LGBT employer. We do not discriminate on the basis of race, gender, or any other protected category, and all decisions we make are made on the basis of qualifications, merit, and business need. Our goal is to be one global team that is representative of our customers, in an inclusive environment where we can continue to innovate and grow together. Please click here: Equal Employment Opportunity . Hewlett Packard Enterprise is EEO Protected Veteran/ Individual with Disabilities. HPE will comply with all applicable laws related to employer use of arrest and conviction records, including laws requiring employers to consider for employment qualified applicants with criminal histories. Recruitment Fraud Alert We have become aware of an increase in fraudulent recruitment activities in which individuals impersonate our company or authorized recruitment agencies to offer fake employment opportunities. These scams may occur through false websites, emails, social media, or chat-based applications and often aim to obtain personal information or money. Please note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge a candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. We also never request personal information such as back account details, Social Security numbers, or national IDs via social media or chat applications. All legitimate job opportunities will come through official company channels, and candidates are responsible for verifying the credentials of any third party claiming to represent the company. Any reliance on fraudulent communication is at the individual’s own risk, and HPE disclaims legal liability for any resulting damages. If you suspect recruitment fraud, do not share personal information or make any payments and report the incident to your local authorities immediately.

Requirements

Must-haves

Sr. ASIC Design Engineer
This role has been designed as 'Hybrid' with a requirement that you will work on average 2 days per week from an HPE office.
Bring your passion and there are no boundaries to what you can accomplish here. We are like a start-up in a big company. Year after year, our group builds the most powerful and highest density networking chips.
Open communications, empowerment, innovation, teamwork, and customer success are the foundations of team culture. Thus, you set your own limits for learning, achievements, and rewards.
You will start with a functional specification of a module and produce a detailed micro-architecture specification that meets the power/area requirements.
You will implement the design using Verilog or System Verilog
Write functional coverage/SVA to help verification catch corner case bugs.
You will work with the Physical Design team for optimal floorplan and timing closure. You will identify and fix timing in RTL to meet the frequency target.
Work with the Verification team to make sure your block is fully validated.
You will have opportunities to improve leadership skills by providing mentoring/guidance to new college-grad engineers and interns.
Recommended skills
Bachelor’s degree in Electrical Engineering required (Master’s strongly desired) with 5 years of relevant experience.
Strong analytical/problem solving skills.
Strong coding skills in Verilog/System Verilog through courses/projects and previous work experience is desired.
Knowledge of synthesis/lint and other state-of-the-art EDA tools is desired.
Excellent written and verbal communications skills are good to have.
Accessibility
Note: This option is reserved for applicants needing assistance/reasonable accommodation related to a disability.
Health & Wellbeing
We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.
Personal & Professional Development

Nice-to-haves

Knowledge of Computer Architecture/networking protocols through graduate level courses or prior work is a plus.
Knowledge of Perl/Python is a plus.
Experience with AI agentic tools is a plus.

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

pythonaiaccessibility

Platform: workday
Effort: long

Benefits

Benefits detected in the listing.

Vision

Professional Development