Job description

Standard Job Description Develops, designs, verifies, and documents Application-Specific Integrated Circuits (ASIC) and Field Programmable Gate Arrays (FPGA) development. Determines architecture design, logic design, and system simulation. Assignments include the analysis of all aspects from high-level design to synthesis, place and route, and timing and power utilization. Typically uses specialized equipment to establish operation data, conduct experimental tests, and evaluate results. Basic Qualifications • Bachelor of Science or higher from an accredited college in Electrical Engineering or related discipline, or equivalent experience/combined education. • Experience or coursework in the verification of FPGA and/or ASIC devices. • HDL programming experience with VHDL, Verilog, and/or SystemVerilog. • Linux environment • Willing and able to obtain and maintain a DoD Secret clearance, thus US Citizenship is required for this position. Desired Skills • Experience or coursework in the verification of FPGA and/or ASIC devices. • Experience or coursework with modern verification methodologies such as UVM, OVM or VMM. • Experience in ASIC / FPGA life cycle (architecture, design, simulation, verification, validation, integration & test). • FPGA/ASIC design experience is a plus. • Experienced in scripting such as Perl, TCL, Python. • Experience leading small teams in technical work, setting priorities, managing schedules • Experience in creating project plans Pay Information Full-Time Salary Range: $75400.00 - $140000.00 At Lockheed Martin, we know mission success starts with taking care of our people. Our Total Rewards program is designed to attract top talent, support your well-being, and help you grow—both professionally and personally. The salary range for this position is as listed on the requisition. Please note that the salary information listed is a general guideline only. Lockheed Martin considers factors such as (but not limited to) scope and responsibilities of the position, candidate's work experience, education/ training, key skills as well as market(work location) and business considerations when extending an offer. Benefits offered: Medical, Dental, Vision, Flexible work arrangements and schedules (e.g., 4x10), 401(k) match, Paid time off, Holidays, Parental Leave, EAP, Flexible Spending Accounts, Education Assistance, Life Insurance, Short-Term Disability, and Long-Term Disability. • Annual short-term and/or long-term incentive compensation programs may be offered depending on the position. Payments under these annual programs are not guaranteed and can vary from year to year and are tied to a range of performance metrics. • For (Washington state applicants only) Non-represented full-time employees: accrue at least 10 hours per month of Paid Time Off (PTO) to be used for incidental absences and other reasons; receive at least 90 hours for holidays. Represented full time employees accrue 6.67 hours of Vacation per month; accrue up to 52 hours of sick leave annually; receive at least 96 hours for holidays. PTO, Vacation, sick leave, and holiday hours are prorated based on start date during the calendar year.

Requirements

Must-haves

Standard Job Description
Bachelor of Science or higher from an accredited college in Electrical Engineering or related discipline, or equivalent experience/combined education.
Experience or coursework in the verification of FPGA and/or ASIC devices.
HDL programming experience with VHDL, Verilog, and/or SystemVerilog.
Linux environment
Willing and able to obtain and maintain a DoD Secret clearance, thus US Citizenship is required for this position.

Nice-to-haves

Experience or coursework in the verification of FPGA and/or ASIC devices.
Experience or coursework with modern verification methodologies such as UVM, OVM or VMM.
Experience in ASIC / FPGA life cycle (architecture, design, simulation, verification, validation, integration & test).
FPGA/ASIC design experience is a plus.
Experienced in scripting such as Perl, TCL, Python.
Experience leading small teams in technical work, setting priorities, managing schedules
Experience in creating project plans
Pay Information

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

python

Platform: eightfold
Effort: medium

Benefits

Benefits detected in the listing.

Dental

Vision

401(K)

Pto

Paid Time Off

Parental Leave