Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them. AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward. THE ROLE We are seeking an experienced SoC Architect to lead the architecture of next-generation Adaptive SoCs. This role spans compute, memory, AI, high-speed I/O, power, clocking, and platform integration, with a strong focus on analog/mixed-signal technologies, advanced packaging, high-speed interface architectures, and system-level design. The architect will drive key silicon, package, and board-level decisions, with particular emphasis on I/O subsystem definition, PHY integration, signal and power integrity considerations, package-board co-design, and platform-level interface optimization to deliver scalable, high-performance, and power-efficient solutions. THE PERSON You are a seasoned SoC architect with deep expertise in heterogeneous compute systems and a strong understanding of end-to-end system design. You bring a system-level perspective that spans digital architecture, analog IP integration, packaging, signal integrity, power delivery, and platform design. You thrive in collaborative environments, excel at navigating complex tradeoffs, and are passionate about delivering innovative solutions that optimize performance, power, area, cost, and scalability. You communicate effectively across engineering disciplines and influence architectural decisions through technical leadership and strategic vision. KEY RESPONSIBILITIES • Define and drive the architecture of key SoC subsystems, including processors, memory subsystems, interconnects, AI engines, GPUs, multimedia blocks, and I/O interfaces, with a focus on performance, power, area, and cost tradeoffs. • Lead SoC integration strategy, including control architecture, reset and boot flows, clocking architecture, power domains, security considerations, and system manageability. • Drive early-stage architectural exploration, workload analysis, performance modeling, and specification development. • Define and evaluate system-level solutions involving analog and mixed-signal IPs, including high-speed SerDes, DDR PHYs, PCIe/CXL PHYs, clocking subsystems, power management circuits, and other I/O technologies. • Collaborate closely with analog, digital, package, and board design teams to ensure robust end-to-end interface architectures and successful platform deployment. • Drive architectural decisions related to signal integrity, power integrity, board-level constraints, interface protocols, and package-board interactions. • Contribute to architectural innovation for Adaptive SoC use cases across AI, data center, embedded, networking, graphics, and multimedia applications. • Partner with hardware, software, validation, product planning, and system teams to develop cohesive architecture solutions and execution plans. • Mentor engineers and contribute to the long-term technical direction of the architecture organization. PREFERRED EXPERIENCE • Proven experience leading SoC architecture for complex processor-based systems with deep knowledge of processor, memory, interconnect, and I/O subsystems. • Strong understanding of analog and mixed-signal IP integration, including high-speed I/O, PHY architectures, SerDes technologies, DDR interfaces, clock generation and distribution, and power management solutions. • Experience with board-level architecture, platform design, signal integrity, power integrity, package interactions, and interface design considerations. • Expertise in industry-standard interfaces and protocols such as PCIe, CXL, Ethernet, USB, UCIe, DDR, LPDDR, HBM, and related technologies. • Expertise in SoC control architecture, reset design, clocking strategies, power management, and system bring-up. • Demonstrated success delivering high-performance, low-power SoC products from concept through production. • Knowledge of advanced process technologies, packaging approaches, and associated design challenges. • Excellent communication, leadership, and cross-functional collaboration skills. ACADEMIC CREDENTIALS • BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field. LOCATION: San Jose, CA This role is not eligible for visa sponsorship. #LI-DR2 Benefits offered are described: AMD benefits at a glance . AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Requirements

Must-haves

ADVANCE YOUR CAREER. ADVANCE THE WORLD.
Lead SoC integration strategy, including control architecture, reset and boot flows, clocking architecture, power domains, security considerations, and system manageability.
Drive early-stage architectural exploration, workload analysis, performance modeling, and specification development.
Define and evaluate system-level solutions involving analog and mixed-signal IPs, including high-speed SerDes, DDR PHYs, PCIe/CXL PHYs, clocking subsystems, power management circuits, and other I/O technologies.
Collaborate closely with analog, digital, package, and board design teams to ensure robust end-to-end interface architectures and successful platform deployment.
Drive architectural decisions related to signal integrity, power integrity, board-level constraints, interface protocols, and package-board interactions.
Contribute to architectural innovation for Adaptive SoC use cases across AI, data center, embedded, networking, graphics, and multimedia applications.
Partner with hardware, software, validation, product planning, and system teams to develop cohesive architecture solutions and execution plans.
Mentor engineers and contribute to the long-term technical direction of the architecture organization.
BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
LOCATION: San Jose, CA
Benefits offered are described: AMD benefits at a glance .
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.

Nice-to-haves

Proven experience leading SoC architecture for complex processor-based systems with deep knowledge of processor, memory, interconnect, and I/O subsystems.
Strong understanding of analog and mixed-signal IP integration, including high-speed I/O, PHY architectures, SerDes technologies, DDR interfaces, clock generation and distribution, and power management solutions.
Experience with board-level architecture, platform design, signal integrity, power integrity, package interactions, and interface design considerations.
Expertise in industry-standard interfaces and protocols such as PCIe, CXL, Ethernet, USB, UCIe, DDR, LPDDR, HBM, and related technologies.
Expertise in SoC control architecture, reset design, clocking strategies, power management, and system bring-up.
Demonstrated success delivering high-performance, low-power SoC products from concept through production.
Knowledge of advanced process technologies, packaging approaches, and associated design challenges.
Excellent communication, leadership, and cross-functional collaboration skills.

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Platform: amd
Effort: medium

Benefits

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