Job description

Snap Inc is a technology company. We believe the camera presents the greatest opportunity to improve the way people live and communicate. Snap contributes to human progress by empowering people to express themselves, live in the moment, learn about the world, and have fun together. The Company operates Snapchat , a visual messaging app that enhances your relationships with friends, family, and the world, and Specs Inc. , a wholly-owned subsidiary dedicated to making computing more human, in addition to Bitmoji , Saturn, and other digital services. Specs Inc. is a wholly-owned subsidiary of Snap Inc. dedicated to making computing more human. The company develops Specs, advanced eyewear that seamlessly integrates digital experiences into the physical world. Specs feature see-through lenses that place digital objects directly into three-dimensional space, powered by Snap OS, a proprietary, context-aware operating system designed for natural interaction with your hands and voice. Specs Inc. also provides Lens Studio, a full suite of advanced developer tools that powers immersive augmented reality experiences across Specs, Snapchat, and other services. The MicroDisplay Electronics and Software team develops state-of-the-art microdisplays for use in Specs. What you’ll do: Work as part of a multi-disciplinary team designing display ICs for AR Work closely with chip architect, verification, analog design, and test functions to design a Big-D,Big-A type ASIC Manage a small team of digital designers and physical design engineers to create RTL code and its physical implementation Execute and Continuously Improve RTL design and RTL-to-gds Digital Implementation flows for our Display ICs Perform or manage RTL-based logic design, Design-for-Test, chip floorplanning, place-and-route, timing closure, physical verification, synthesis, DFT insertion, LEC Specify and configure tools and create automation Hire and manage additional new staff This position may initially include individual contributor work, until the group expands further Knowledge, Skills & Abilities: People management skills and knowledge of typical HR policies and procedures, including performance management, hiring, firing, and promotion Strong working knowledge of logic design and RTL coding and associated functions (lint, CDC, LEC, DFT) Strong working knowledge of digital implementation (physical design) Strong working knowledge of integration of external and internal design IP, including analog blocks Strong working knowledge of Cadence Innovus, Tempus, Genus and PVS tools or equivalents Strong working knowledge of Mentor/Siemens Calibre tool suite Scripting and automation, such as TCL, SKILL, Perl, Python and Shell scripts Minimum Qualifications: BSEE or MSEE 10 years in directly applicable work performing physical design / digital implementation Minimum of 3 years experience in a management role Optional – see preferred Qualifications Preferred Qualifications: Knowledge of Analog, Mixed-signal circuit design and custom layout Knowledge of Siemens QuestaSim (formerly Modelsim) Knowledge of emulation, and the Siemens Veloce Emulator Knowledge of Cadence Innovus, Genus, Tempus tools Knowledge of Tessent DFT tools Knowledge of Conformal LEC tool or equivalent Knowledge of Virtuoso custom layout tool or equivalent Default Together Policy at Snap: At Snap Inc. we believe that being together in person helps us build our culture faster, reinforce our values, and serve our community, customers and partners better through dynamic collaboration. To reflect this, we practice a “default together” approach and expect our team members to work in an office 4 days per week. At Snap, we believe that having a team of diverse backgrounds and voices working together will enable us to create innovative products that improve the way people live and communicate. Snap is proud to be an equal opportunity employer, and committed to providing employment opportunities regardless of race, religious creed, color, national origin, ancestry, physical disability, mental disability, medical condition, genetic information, marital status, sex, gender, gender identity, gender expression, pregnancy, childbirth and breastfeeding, age, sexual orientation, military or veteran status, or any other protected classification, in accordance with applicable federal, state, and local laws. EOE, including disability/vets. We are an Equal Opportunity Employer and will consider qualified applicants with criminal histories in a manner consistent with applicable law (by example, the requirements of the San Francisco Fair Chance Ordinance and the Los Angeles Fair Chance Initiative for Hiring, where applicable). Our Benefits : Snap Inc. is its own community, so we’ve got your back! We do our best to make sure you and your loved ones have everything you need to be happy and healthy, on your own terms. Our benefits are built around your needs and include paid parental leave, comprehensive medical coverage, emotional and mental health support programs, and compensation packages that let you share in Snap’s long-term success! Compensation In the United States, work locations are assigned a pay zone which determines the salary range for the position. The successful candidate’s starting pay will be determined based on job-related skills, experience, qualifications, work location, and market conditions. The starting pay may be negotiable within the salary range for the position. These pay zones may be modified in the future. Zone A (CA, WA, NYC) : The base salary range for this position is $229,000-$343,000 annually. Zone B : The base salary range for this position is $218,000-$326,000 annually. Zone C : The base salary range for this position is $195,000-$292,000 annually. This position is eligible for equity in the form of RSUs. If you believe this job description is missing required pay transparency information, please submit a report through this form : Job Description Pay Range Disclosure .

Requirements

Must-haves

The MicroDisplay Electronics and Software team develops state-of-the-art microdisplays for use in Specs.
Work as part of a multi-disciplinary team designing display ICs for AR
Work closely with chip architect, verification, analog design, and test functions to design a Big-D,Big-A type ASIC
Manage a small team of digital designers and physical design engineers to create RTL code and its physical implementation
Execute and Continuously Improve RTL design and RTL-to-gds Digital Implementation flows for our Display ICs
Perform or manage RTL-based logic design, Design-for-Test, chip floorplanning, place-and-route, timing closure, physical verification, synthesis, DFT insertion, LEC
Specify and configure tools and create automation
Hire and manage additional new staff
This position may initially include individual contributor work, until the group expands further
People management skills and knowledge of typical HR policies and procedures, including performance management, hiring, firing, and promotion
Strong working knowledge of logic design and RTL coding and associated functions (lint, CDC, LEC, DFT)
Strong working knowledge of digital implementation (physical design)
Strong working knowledge of integration of external and internal design IP, including analog blocks
Strong working knowledge of Cadence Innovus, Tempus, Genus and PVS tools or equivalents
Strong working knowledge of Mentor/Siemens Calibre tool suite
Scripting and automation, such as TCL, SKILL, Perl, Python and Shell scripts

Nice-to-haves

Optional – see preferred Qualifications
Knowledge of Analog, Mixed-signal circuit design and custom layout
Knowledge of Siemens QuestaSim (formerly Modelsim)
Knowledge of emulation, and the Siemens Veloce Emulator
Knowledge of Cadence Innovus, Genus, Tempus tools
Knowledge of Tessent DFT tools
Knowledge of Conformal LEC tool or equivalent
Knowledge of Virtuoso custom layout tool or equivalent

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

python

Platform: workday
Effort: long

Benefits

Benefits detected in the listing.

Parental Leave