Job description

Annapurna Labs designs the custom silicon that powers AWS's machine learning infrastructure, including the Trainium and Inferentia chip families. Our next-generation ML accelerator is a multi-die chiplet using state-of-the-art packaging technology, and it is the most complex hardware program Amazon has undertaken. We are looking for a Principal Technical Program Manager to own end-to-end program execution for this chip, from RTL freeze through tape-out and into production readiness. This is not a status-reporting role. You will be the person who connects a sprawling set of engineering workstreams into a single coherent schedule, identifies the real critical path week to week, and drives the cross-functional decisions that keep the program on track. The program spans multiple concurrent silicon development efforts with significant interdependencies across engineering disciplines, external partners, and infrastructure. Key job responsibilities Own the integrated schedule and critical path analysis across multiple die tape-outs through engineering samples and production ramp. Understand dependency chains deeply enough to calculate the impact of any slip or pull-in, and update the timeline weekly with real data. Drive the weekly chip status cadence by synthesizing inputs from RTL/DV, physical design, packaging, power, infrastructure, and post-silicon teams into a single view that tells leadership where we actually stand, including what is getting worse and what needs action. Track verification convergence as a leading indicator by monitoring the progression from feature completion through RTL closure, bug trends, and regression pass rates by block. Recognize when convergence is stalling and drive the engineering response before downstream milestones are affected. Manage the external design partner interface, owning the netlist delivery calendar, tracking your partner's physical design timeline, and negotiating schedule trades with a clear understanding of downstream cost. Drive infrastructure readiness and external IP delivery by partnering with compute and EDA platform teams on capacity planning, and tracking third-party PHY, memory interface, and controller IP deliveries against consuming blocks to escalate gaps before they become tape-out critical. A day in the life You start your morning reviewing verification convergence dashboards and regression results, spotting a block where bug closure rates haven't flattened. You pull the DV lead and RTL owner into a quick sync to agree on a recovery plan before the weekly chip status review. In that review, you walk leadership through an updated critical path that reflects a netlist delivery shift from your external design partner, quantifying the downstream impact on tape-out timing. After lunch, you join an infrastructure capacity review to confirm that compute clusters can handle the regression load through freeze, then close out the day preparing an executive summary for an upcoming program milestone review. About the team The Annapurna Labs ML Accelerator team builds the Trainium and Inferentia silicon that trains and serves machine learning models across AWS. We work at the intersection of chip architecture, physical design, verification, and infrastructure to deliver products that push the boundaries of performance and efficiency for our customers. Our team values people who bring strong technical judgment, clear communication, and a willingness to get into the details. If you want to shape how Amazon builds its most ambitious hardware and work alongside talented engineers solving real problems at scale, this is the role for you. - 10+ years of hands-on work managing complex technology projects experience - 10+ years of working directly with engineering teams experience - Deep working knowledge of the chip development lifecycle: RTL verification milestones, physical design convergence, DFT, and timing closure. - Experience managing programs with external design partners and IP vendors where you don't control the resources but own the outcome. - Demonstrated ability to build and maintain integrated schedules with real dependency modeling — not just Gantt charts, but an understanding of which paths have float and which don't. - Strong technical communication skills: ability to present crisp status to VP-level audiences, distinguishing signal from noise, and framing decisions clearly. - Experience with multi-die / chiplet / advanced packaging programs (2.5D/3D integration). - Familiarity with HBM integration, die-to-die interfaces, or high-speed serial subsystems. - Experience with leading-edge foundry nodes and their specific flow and schedule characteristics. - Background in ML accelerator or high-performance compute silicon. - Experience driving infrastructure capacity planning for large-scale chip development programs. Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit amazon.jobs for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner. The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at amazon.jobs . USA, CA, Cupertino - 203,500.00 - 275,300.00 USD annually USA, TX, Austin - 177,000.00 - 239,400.00 USD annually

Requirements

Must-haves

Key job responsibilities
Manage the external design partner interface, owning the netlist delivery calendar, tracking your partner's physical design timeline, and negotiating schedule trades with a clear understanding of downstream cost.
A day in the life
About the team
10+ years of hands-on work managing complex technology projects experience
10+ years of working directly with engineering teams experience
Deep working knowledge of the chip development lifecycle: RTL verification milestones, physical design convergence, DFT, and timing closure.
Experience managing programs with external design partners and IP vendors where you don't control the resources but own the outcome.
Demonstrated ability to build and maintain integrated schedules with real dependency modeling — not just Gantt charts, but an understanding of which paths have float and which don't.
Strong technical communication skills: ability to present crisp status to VP-level audiences, distinguishing signal from noise, and framing decisions clearly.
Experience with multi-die / chiplet / advanced packaging programs (2.5D/3D integration).
Familiarity with HBM integration, die-to-die interfaces, or high-speed serial subsystems.
Experience with leading-edge foundry nodes and their specific flow and schedule characteristics.
Background in ML accelerator or high-performance compute silicon.
Experience driving infrastructure capacity planning for large-scale chip development programs.
Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.
USA, CA, Cupertino - 203,500.00 - 275,300.00 USD annually
USA, TX, Austin - 177,000.00 - 239,400.00 USD annually

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Keywords to mirror

awsmachine learningml

Platform: amazon
Effort: medium

Benefits

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Health Insurance

Dental

Vision

401(K)

Paid Time Off

Parental Leave