Job description

SambaNova is a leader in next-generation AI infrastructure, delivering a full-stack inference platform for customers worldwide. At the core of SambaNova's technology is the RDU (Reconfigurable Dataflow Unit) — a chip built on a dataflow architecture rather than the traditional GPU model. Its decode performance is especially strong for agentic workloads like multi-turn agents, code generation, and long-running applications. RDUs are packaged into SambaRack, rack-scale hardware that lets customers deploy state-of-the-art models with better performance, greater energy efficiency, and faster time to value. About the team SambaNova's RDU is the processor behind our inference systems, and design verification ensures quality and reliability before production. The team owns verification for block, full-chip, and gate-level benches, performance verification, coverage closure, and the emulation and FPGA prototypes. About the role SambaNova is looking for a Principal Design Verification Engineer to own verification for our next-generation RDU, the reconfigurable dataflow silicon behind our machine learning and AI systems. This is a senior individual-contributor role where you'll own the test plan, testbench architecture, coverage model, and sign-off criteria, while shaping the team-wide infrastructure, reuse patterns, and verification practices. You'll work alongside principal engineers from the design, architecture, compiler, and runtime teams who have built and evolved this verification environment across several generations of silicon, to verify the chip against production ML workloads. Responsibilities Some of your responsibilities will include... Own verification end to end for a major subsystem of the RDU: test plan, testbench architecture, coverage model, and sign-off criteria Build the coverage model for your area, set the closure bar, and drive it to closure ahead of tape-out Develop testbench components, agents, checkers, and stimulus at block, full-chip, system, and gate level Serve as the technical authority for verification of your subsystem: review and arbitrate testbench design decisions, and lead debug on the hardest failures Own regression health and failure triage for your area: drive root cause, not just reproduction Verify functional and performance behavior Advance DV methodology beyond your own area: reusable infrastructure, verification IP integration, and AI-assisted verification workflows the rest of the team adopts Contribute to emulation and FPGA prototyping, and support silicon bring-up and post-silicon debug in the lab Set the technical bar through design and DV reviews, and mentor engineers to raise the level of the team's verification practice Required qualifications BS or MS in EE, CS, or CE with 7+ years (or equivalent) of industry experience in ASIC design verification Deep hands-on expertise in SystemVerilog and SVA with a standard methodology (UVM, OVM, or VMM), plus scripting in Python and C/C++ Full-cycle DV ownership from test plan through tape-out on at least one complex ASIC or major subsystem, including owning a coverage model to closure Experience verifying digital logic in a CPU, GPU, SoC, or comparably complex ASIC Track record of debugging hard, intermittent, or low-reproducibility pre-silicon failures to root cause Demonstrated technical leadership without formal authority: setting direction in reviews, arbitrating testbench decisions, and mentoring engineers Working knowledge of modern computer architecture and of machine learning accelerators or SoCs Preferred qualifications MS or PhD in EE, CS, or CE with 10+ years of experience in ASIC design verification Depth in high-speed I/O verification: protocol-level verification of PCIe or Ethernet, and memory subsystems such as HBM or DDR Performance verification methodology: building performance benches and analyzing results, not only functional correctness Formal verification and assertion-based methods Experience evaluating, integrating, and validating third-party verification IP Gate-level simulation and debug Emulation and FPGA prototyping platforms Post-silicon lab bring-up and functional validation, debugging first-silicon issues to root cause Strong understanding of one or more of computation, interconnect, or memory systems Fluency with Claude or other AI tools applied to verification and flow development Base Salary Range: Base Pay Range $180,000 — $255,000 USD Submission Guidelines Please note that in order to be considered an applicant for any position at SambaNova Systems, you must submit an application form for each position for which you believe you are qualified. EEO Policy SambaNova Systems is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard basis of age (40 and over), color, disability, gender identity, genetic information, marital status, military or veteran status, national origin/ancestry, race, religion, creed, sex (including pregnancy, childbirth, breastfeeding), sexual orientation, and any other applicable status protected by federal, state, or local laws. Benefits Summary for US-Based, Full-Time Employment Positions SambaNova offers a competitive total rewards package, including the base salary, plus equity and benefits. We cover 95% premium coverage for employee medical insurance, and 77% premium coverage for dependents and offer a Health Savings Account (HSA) with employer contribution. We also offer Dental, Vision, Short/Long term Disability, Basic Life, Voluntary Life, and AD&D insurance plans in addition to Flexible Spending Account (FSA) options like Health Care, Limited Purpose, and Dependent Care. Our library of well-being benefits available to you and your dependents includes a full subscription to Headspace, Gympass+ membership with access to physical gyms, One Medical membership, counseling services with an Employee Assistance Program, and much more.

Requirements

Must-haves

Some of your responsibilities will include...
Own verification end to end for a major subsystem of the RDU: test plan, testbench architecture, coverage model, and sign-off criteria
Build the coverage model for your area, set the closure bar, and drive it to closure ahead of tape-out
Develop testbench components, agents, checkers, and stimulus at block, full-chip, system, and gate level
Serve as the technical authority for verification of your subsystem: review and arbitrate testbench design decisions, and lead debug on the hardest failures
Own regression health and failure triage for your area: drive root cause, not just reproduction
Verify functional and performance behavior
Advance DV methodology beyond your own area: reusable infrastructure, verification IP integration, and AI-assisted verification workflows the rest of the team adopts
Contribute to emulation and FPGA prototyping, and support silicon bring-up and post-silicon debug in the lab
Set the technical bar through design and DV reviews, and mentor engineers to raise the level of the team's verification practice
BS or MS in EE, CS, or CE with 7+ years (or equivalent) of industry experience in ASIC design verification
Deep hands-on expertise in SystemVerilog and SVA with a standard methodology (UVM, OVM, or VMM), plus scripting in Python and C/C++
Full-cycle DV ownership from test plan through tape-out on at least one complex ASIC or major subsystem, including owning a coverage model to closure
Experience verifying digital logic in a CPU, GPU, SoC, or comparably complex ASIC
Track record of debugging hard, intermittent, or low-reproducibility pre-silicon failures to root cause

Nice-to-haves

Depth in high-speed I/O verification: protocol-level verification of PCIe or Ethernet, and memory subsystems such as HBM or DDR
Performance verification methodology: building performance benches and analyzing results, not only functional correctness
Formal verification and assertion-based methods
Experience evaluating, integrating, and validating third-party verification IP
Gate-level simulation and debug
Emulation and FPGA prototyping platforms
Post-silicon lab bring-up and functional validation, debugging first-silicon issues to root cause
Strong understanding of one or more of computation, interconnect, or memory systems
Fluency with Claude or other AI tools applied to verification and flow development

Application prep

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Keywords to mirror

aimachine learningmlrestpython

Platform: greenhouse
Effort: quick

Benefits

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Dental

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