Job description

We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world! We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive. Our Purpose At Teradyne, we develop advanced semiconductor test and automation solutions that enable the next generation of electronic technologies. Our Silicon Technology Engineering (STE) organization designs high-performance ASICs that power industry-leading semiconductor test systems used by the world's leading chip manufacturers. We foster a culture of innovation, collaboration, and continuous learning where engineers solve complex technical challenges that directly influence the future of technology. Opportunity Overview Teradyne's Digital ASIC Group is seeking a Senior RTL Digital Design Engineer to help develop complex mixed-signal ASICs for next-generation semiconductor test systems. Working closely with architects, analog designers, verification engineers, and physical design teams, you will drive digital design activities from architecture definition through silicon bring-up. This role offers the opportunity to own critical ASIC subsystems, influence technical direction, and contribute to cutting-edge products in a highly collaborative environment. Required Qualifications • BSEE required; MSEE or PhD desired. • 8+ years of ASIC or digital design experience with strong expertise in Verilog/SystemVerilog RTL development. • Proven experience designing complex digital blocks including state machines, FIFOs, high-speed datapaths, arbitration logic, and DFT-friendly architectures. • Strong knowledge of ASIC development flows including synthesis, static timing analysis (STA), clock domain crossing (CDC), and timing closure. • Experience integrating third-party and custom IP into large-scale SoCs or mixed-signal ASICs. • Proficiency with scripting and automation using Python, Tcl, Make, or similar languages. • Experience supporting verification, silicon bring-up, debugging, and root-cause analysis. • Strong collaboration, communication, and problem-solving skills with the ability to mentor junior engineers and drive technical excellence across cross-functional teams. Compensation: The base salary range for this role is $192,300 - $307,600. This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location. Incentive Plan: This job is eligible for discretionary bonus(es) based on financial performance. Benefits : Teradyne offers a variety of comprehensive health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more. Please click here to see details. We are an equal-opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform crucial job functions, and to receive other benefits and privileges of employment. #LI-MD1

Requirements

Must-haves

Opportunity Overview
BSEE required; MSEE or PhD desired.
8+ years of ASIC or digital design experience with strong expertise in Verilog/SystemVerilog RTL development.
Proven experience designing complex digital blocks including state machines, FIFOs, high-speed datapaths, arbitration logic, and DFT-friendly architectures.
Strong knowledge of ASIC development flows including synthesis, static timing analysis (STA), clock domain crossing (CDC), and timing closure.
Experience integrating third-party and custom IP into large-scale SoCs or mixed-signal ASICs.
Proficiency with scripting and automation using Python, Tcl, Make, or similar languages.
Experience supporting verification, silicon bring-up, debugging, and root-cause analysis.
Strong collaboration, communication, and problem-solving skills with the ability to mentor junior engineers and drive technical excellence across cross-functional teams.

Nice-to-haves

Incentive Plan: This job is eligible for discretionary bonus(es) based on financial performance.

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python

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Effort: medium

Benefits

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Dental

Vision