Job Functions
Develop FPGA Design Verification tests, and test plans
Review Detailed Design specifications for logic to be tested
Execute tests, analyze results, review RTL, determine probably source of failures, write bug reports
Work with IP vendors and Design engineers to resolve bugs
Desired Skills and Experience
Expertise in ASIC or FPGA RTL design verification
Expertise in system Verilog, and UVM
Strong experience in software design, using classes
Developed and used scripting languages such as TCL, Perl, and Python
Experience with bug tracking (e.g. bugzilla), revision control (e.g. git), and build systems (e.g. make)
Working knowledge of logic design using RTL techniques
Familiar with Protocols and VIPs for PCIe, Ethernet, DRAM
Ability to interface with other disciplines, includng RTL/Logic, hardware design, and firmware engineers
Qualifications:
BS, MS CS, EE or related discipline, or 7+ years of equivalent experience
History of solving technical problems, solo and in a team
Excellent written and oral communication skills
All your information will be kept confidential according to EEO guidelines.