Job description

Job Details: Job Description: The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow s technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people s digital lives. Come join us and do something wonderful. The Role and Impact: As a GPU Physical Design Engineer, you will play a critical role in the physical implementation of cutting-edge GPU designs from RTL to GDS, ensuring optimal performance, power, and area. You will be responsible for executing key aspects of the physical design flow, including synthesis, place and route, timing analysis, and verification, driving the success of Intel s next-generation graphics products. Business group: You will join Intel s Data Center Group (DCG), a team dedicated to creating innovative technologies for data center and enterprise solutions. DCG focuses on delivering high-performance computing systems, enabling Intel s mission to advance data-driven insights and empower businesses worldwide. The primary responsibilities for this role will include, but are not limited to: Perform physical design implementation of GPU designs, including synthesis, placement, routing, and clock tree synthesis. Conduct verification and signoff tasks, such as static timing analysis, layout verification, and formal equivalence checking. Analyze results and collaborate with cross-functional teams to optimize design for power, frequency, and area. Develop and improve physical design methodologies and flow automation for continuous innovation in GPU physical design. Address GPU development challenges by defining product requirements and implementing tailored methodologies for advanced process nodes. Qualifications: Experience listed below would be obtained through a combination of your degree, research and or relevant previous job and or internship experiences. Minimum Qualifications : Minimum qualifications are required to be initially considered for this position. Bachelor s degree in Electrical Engineering, Computer Engineering, or a related field with 6 years of relevant experience, or Master s degree with 4 years of experience, or PhD with 2 years of experience. Experience with ASIC design flows such as floorplanning, synthesis, place and route, and layout verification. Advanced experience in industry-standard tools such as Fusion Compiler, Genus/Innovus, ICC-DP, PrimeTime, StarRC, and Formality. Advanced scripting skills in Tcl, Python, or similar languages for flow automation and optimization. Minimum Qualifications : Minimum qualifications are required to be initially considered for this position. Experience with GPU physical design challenges, including SoC integration and timing closure. Background in optimizing power, performance, and area for designs on advanced process nodes. Familiarity with Unix/Linux-based environments and methodologies for tool and flow development. We are excited to welcome individuals who are passionate about pushing technical boundaries and contributing to the creation of world-class graphics solutions. Join us in driving innovation and shaping the future of computing. Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, California, Folsom Additional Locations: US, California, Santa Clara, US, Oregon, Hillsboro Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel . Annual Salary Range for jobs which could be performed in the US: $164,470.00-232,190.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Requirements

Must-haves

The primary responsibilities for this role will include, but are not limited to:
Perform physical design implementation of GPU designs, including synthesis, placement, routing, and clock tree synthesis.
Conduct verification and signoff tasks, such as static timing analysis, layout verification, and formal equivalence checking.
Analyze results and collaborate with cross-functional teams to optimize design for power, frequency, and area.
Develop and improve physical design methodologies and flow automation for continuous innovation in GPU physical design.
Address GPU development challenges by defining product requirements and implementing tailored methodologies for advanced process nodes.
Qualifications: Experience listed below would be obtained through a combination of your degree, research and or relevant previous job and or internship experiences.
Minimum qualifications are required to be initially considered for this position.
Bachelor s degree in Electrical Engineering, Computer Engineering, or a related field with 6 years of relevant experience, or Master s degree with 4 years of experience, or PhD with 2 years of experience.
Experience with ASIC design flows such as floorplanning, synthesis, place and route, and layout verification.
Advanced experience in industry-standard tools such as Fusion Compiler, Genus/Innovus, ICC-DP, PrimeTime, StarRC, and Formality.
Advanced scripting skills in Tcl, Python, or similar languages for flow automation and optimization.
Minimum qualifications are required to be initially considered for this position.
Experience with GPU physical design challenges, including SoC integration and timing closure.
Background in optimizing power, performance, and area for designs on advanced process nodes.
Familiarity with Unix/Linux-based environments and methodologies for tool and flow development.
Job Type: Experienced Hire
Shift: Shift 1 (United States of America)
Primary Location: US, California, Folsom
Additional Locations: US, California, Santa Clara, US, Oregon, Hillsboro

Nice-to-haves

None flagged.

Application prep

Use the role’s language and application details while tailoring your materials.

Keywords to mirror

python

Platform: workday
Effort: long