Job description

In this role you will work on a small team designing CPU-based subsystems for high performance, low power wireless SoCs. As a member of the team, you will work closely with SoC architects and IP developers to develop SoCs that meet the power, performance, and area goals for Apple devices, with a particular focus on low power metrics. You will engage in hardware/software/power partitioning discussions alongside software, firmware, and platform engineering teams. You will integrate industry standard and custom hardware IPs into SoCs. This is a highly visible role, where you will be at the center of the ASIC design efforts, collaborating with all fields, with a critical impact in getting leading-edge products launched to delight millions of customers. Minimum requirement of a bachelors degree. Familiarity with the ASIC design flow. Knowledge of digital design, SoC architecture, and HDL languages like Verilog. MSEE with some years of industry experience Shown experience writing micro-architecture specifications and converting them to design Exposure to design methodologies and industry standard EDA tools. Experience with AXI/AHB bus fabric and processor sub-systems. Understanding of UPF and low-power design & implementation techniques. Self-starter and willingness to learn.

Requirements

Must-haves

Minimum requirement of a bachelors degree.
Familiarity with the ASIC design flow.
Knowledge of digital design, SoC architecture, and HDL languages like Verilog.
MSEE with some years of industry experience
Shown experience writing micro-architecture specifications and converting them to design
Exposure to design methodologies and industry standard EDA tools.
Experience with AXI/AHB bus fabric and processor sub-systems.
Understanding of UPF and low-power design & implementation techniques.
Self-starter and willingness to learn.

Nice-to-haves

None flagged.

Application prep

Use the role’s language and application details while tailoring your materials.

Platform: apple
Effort: medium