Job description

MEMBER OF TECHNICAL STAFF - PARTNER INFERENCE ENGINEER ABOUT LIQUIDAI Spun out of MIT CSAIL, we build general-purpose AI systems that run efficiently across deployment targets, from data center accelerators to on-device hardware, ensuring low latency, minimal memory usage, privacy, and reliability. We partner with enterprises across consumer electronics, automotive, life sciences, and financial services. We are scaling rapidly and need exceptional people to help us get there. THE OPPORTUNITY Our thesis is that Liquid Foundation Models unlock the capabilities of the silicon they run on, across GPU, NPU and CPU. Multiple silicon players are shipping hardware to us so LFMs can be profiled on it and taken to market together. Nobody owns that work today. We need an engineer who can lower our models onto partner silicon, profile them, and turn the results into evidence that partners and their customers can use. You will be the first hire of this kind and will build the partner silicon program from scratch: the device lab, the profiling process, and the technical relationship with partner engineering teams. Roughly 70 percent of the role is hands-on technical; the rest is partner- and customer-facing, with automotive OEMs first and PC OEMs next. You will work daily with our Edge Inference team, who own the runtime fixes you flag. This role is based in Boston or San Francisco. You own physical hardware, so remote is not an option. WHAT WE'RE LOOKING FOR We need someone who: - Understands the silicon: Knows how NPU, GPU and CPU blocks on an edge SoC are composed, how a model gets lowered onto them, and why a chip vendor wants a model partner. - Has done it, not planned it: Has personally taken models onto edge hardware, measured latency, power and thermal, and can explain where performance was lost. - Wants the partner-facing work: Can be put in front of a partner's customer engineers or an OEM buyer, co-create a demo, and read their incentives. If you want to work purely on fundamentals, this is the wrong role, and we would rather say so now. - Owns ambiguity: There is no process for partner profiling. You design it, make the silicon work as it is, and hand clear diagnoses to Edge Inference rather than working around them. THE WORK - Own and manage the partner device lab: every SoC that Qualcomm, AMD, Intel, NVDA as well as other chip makers building SoCs for edge and physical AI devices ship us - Lower LFMs onto partner silicon and profile speed, latency, power and thermal - Work directly with partner customer engineers to co-create demos and benchmark narratives - Present results to partners and demand-side buyers, explaining why LFMs on their silicon beat the alternative - Flag model and runtime performance gaps to Edge Inference with a clear hardware-level diagnosis they can act on - Where capability allows, contribute to runtime and model-level optimization directly DESIRED EXPERIENCE Must-have: - Deploying and profiling ML models on at least one edge SoC family (Qualcomm Snapdragon / Hexagon, AMD Ryzen AI / XDNA, Intel NPU, SiMa.ai sima.ai MLSoC, or comparable) - Working knowledge of at least one vendor lowering and runtime toolchain (Qualcomm AI Engine Direct / QNN, SiMa Palette, OpenVINO, ONNX Runtime execution providers, or similar) - On-device performance measurement: latency, throughput, power and thermal - Comfortable presenting technical results to external engineers and commercial stakeholders Nice-to-have: - Breadth across two or more chipset families - Experience inside a chip vendor's customer-engineering, field-application or AI-enablement team - Runtime or kernel-level optimization experience WHAT SUCCESS LOOKS LIKE (YEAR ONE) - LFMs are lowered and profiled on flagship chipsets from multiple silicon partners, with results packaged so the partner's own field teams can use them - A working device lab and repeatable profiling process benchmarks new chipsets within weeks of arrival, not on Edge Inference's bandwidth - Co-created demos are in active use in automotive and PC OEM conversations, and at least one qualified pipeline customer has come to Liquid through a silicon partner WHAT WE OFFER - Impact at the core of the company: This is where Liquid's thesis gets proven on real hardware, with the four biggest edge silicon names shipping chips to us to find out. - Compensation: Competitive base salary with equity in a unicorn-stage company - Health: We pay 100% of medical, dental, and vision premiums for employees and dependents - Financial: 401(k) matching up to 4% of base pay - Time Off: Unlimited PTO plus company-wide Refill Days throughout the year

Requirements

Must-haves

MEMBER OF TECHNICAL STAFF - PARTNER INFERENCE ENGINEER
Understands the silicon: Knows how NPU, GPU and CPU blocks on an edge SoC are composed, how a model gets lowered onto them, and why a chip vendor wants a model partner.
Has done it, not planned it: Has personally taken models onto edge hardware, measured latency, power and thermal, and can explain where performance was lost.
Owns ambiguity: There is no process for partner profiling. You design it, make the silicon work as it is, and hand clear diagnoses to Edge Inference rather than working around them.
Own and manage the partner device lab: every SoC that Qualcomm, AMD, Intel, NVDA as well as other chip makers building SoCs for edge and physical AI devices ship us
Lower LFMs onto partner silicon and profile speed, latency, power and thermal
Work directly with partner customer engineers to co-create demos and benchmark narratives
Present results to partners and demand-side buyers, explaining why LFMs on their silicon beat the alternative
Flag model and runtime performance gaps to Edge Inference with a clear hardware-level diagnosis they can act on
Where capability allows, contribute to runtime and model-level optimization directly
Deploying and profiling ML models on at least one edge SoC family (Qualcomm Snapdragon / Hexagon, AMD Ryzen AI / XDNA, Intel NPU, SiMa.ai http://SiMa.ai MLSoC, or comparable)
Working knowledge of at least one vendor lowering and runtime toolchain (Qualcomm AI Engine Direct / QNN, SiMa Palette, OpenVINO, ONNX Runtime execution providers, or similar)
On-device performance measurement: latency, throughput, power and thermal
Comfortable presenting technical results to external engineers and commercial stakeholders
LFMs are lowered and profiled on flagship chipsets from multiple silicon partners, with results packaged so the partner's own field teams can use them
A working device lab and repeatable profiling process benchmarks new chipsets within weeks of arrival, not on Edge Inference's bandwidth
Co-created demos are in active use in automotive and PC OEM conversations, and at least one qualified pipeline customer has come to Liquid through a silicon partner

Nice-to-haves

Breadth across two or more chipset families
Experience inside a chip vendor's customer-engineering, field-application or AI-enablement team
Runtime or kernel-level optimization experience

Application prep

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Keywords to mirror

airestml

Platform: ashby
Effort: quick

Benefits

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Dental

Vision

401(K)

Pto