Job description

Principal FPGA Engineer Location: Cedar Rapids, IA Job ID: #73379 Duration: 6+months contract Pay Range: $60-71 - W2 hourly Job Description: Seeking a highly skilled and innovative Principal FPGA Engineering Contractor to work with our Applied Research and Technology (ART) Microelectronics Technology team. Your work will contribute to the development of cutting-edge defense solutions across Mission Systems, leveraging your expertise in the design, implementation, verification, and integration of a wide variety of high-performance digital FPGAs. What You Will Do: • Adhere to all applicable Engineering Development and Quality processes, procedures, instructions and guidelines. • Participate in Agile team meetings and planning activities, as required to support programs covered by this work plan. • Requirements, design and verification of FPGA solutions • Integration of developed FPGA on target hardware units • Supporting peer reviews and certification analysis activities • Peer reviewing FPGA development artifacts • Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA design flow • Contribute to engineering estimates for new program pursuits. • Provide technical leadership for project design teams by breaking down work, planning activities, and reporting status Qualifications You Must Have: • Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and minimum 8 years prior relevant experience or an Advanced Degree in a related field and minimum 5 years of experience. • A minimum of 5 years professional experience in FPGA development, ASIC front end, or related areas • Proficient in VHDL/Verilog for FPGA/ASIC design and implementation. • Experience in digital circuit architecture, design, resource tradeoffs, timing analysis, and timing closure • Familiarity with FPGA platforms such as AMD/Xilinx, Altera, Microchip, or others, and associated toolchains (e.g., Vivado, Quartus, Libero). • Strong debugging and troubleshooting skills for FPGA/ASIC systems. • Proficiency with revision control concepts and tools (e.g., Git, Subversion) Qualifications We Prefer: • Excellent communication and teamwork skills with the ability to work in a collaborative environment. • Experience with high-speed digital interfaces and protocols (e.g., DDR, PCIe, Ethernet). • Familiarity with best-practice chip-level verification techniques and languages (e.g., constrained random, functional coverage, System Verilog) • Experience in ASIC / FPGA lab validation using advanced laboratory equipment • Experience with Unix, scripting, C/C++, and/or Perl Citizenship – US Citizen only Benefits provided: 401K, medical, dental, and vision, sick time as applicable to state law Butler America Aerospace, LLC. is an equal opportunity employer. Butler evaluates applicants without regard to race, color, religion, sex, age, national origin, disability, veteran status, genetic information and other legally protected characteristics. The Butler America Aerospace, LLC. EEO Policy Statement and “Know Your Rights” Poster is available here: Applicant and Employee Notices. Butler America Aerospace, LLC. is committed to working with and providing reasonable accommodations to individuals with disabilities. If you need a reasonable accommodation because of a disability for any part of the employment process, please contact the Human Resources Department at accommodations@butler.com .

Requirements

Must-haves

Principal FPGA Engineer
Location: Cedar Rapids, IA
Job ID: #73379
Duration: 6+months contract
Adhere to all applicable Engineering Development and Quality processes, procedures, instructions and guidelines.
Participate in Agile team meetings and planning activities, as required to support programs covered by this work plan.
Requirements, design and verification of FPGA solutions
Integration of developed FPGA on target hardware units
Supporting peer reviews and certification analysis activities
Peer reviewing FPGA development artifacts
Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA design flow
Contribute to engineering estimates for new program pursuits.
Provide technical leadership for project design teams by breaking down work, planning activities, and reporting status
Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and minimum 8 years prior relevant experience or an Advanced Degree in a related field and minimum 5 years of experience.
A minimum of 5 years professional experience in FPGA development, ASIC front end, or related areas
Proficient in VHDL/Verilog for FPGA/ASIC design and implementation.
Experience in digital circuit architecture, design, resource tradeoffs, timing analysis, and timing closure
Familiarity with FPGA platforms such as AMD/Xilinx, Altera, Microchip, or others, and associated toolchains (e.g., Vivado, Quartus, Libero).
Strong debugging and troubleshooting skills for FPGA/ASIC systems.
Proficiency with revision control concepts and tools (e.g., Git, Subversion)
Excellent communication and teamwork skills with the ability to work in a collaborative environment.
Experience with high-speed digital interfaces and protocols (e.g., DDR, PCIe, Ethernet).
Familiarity with best-practice chip-level verification techniques and languages (e.g., constrained random, functional coverage, System Verilog)
Experience in ASIC / FPGA lab validation using advanced laboratory equipment

Nice-to-haves

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Application prep

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Keywords to mirror

agile

Platform: bullhorn
Effort: medium

Benefits

Benefits detected in the listing.

Dental

Vision

401k