Package Layout Design Engineer , Annapurna Labs - AI Silicon Packaging

• We are seeking a Package Layout Design Engineer to join our hardware team and contribute to the physical design of advanced IC packages for next-generation machine learning and data center ASICs.
• Key job responsibilities
• Execute package layout tasks across the design cycle: die floor planning, bump/pad assignment, RDL routing, substrate design, verification, and tape out release.
• Implement physical designs for advanced packaging architectures including 2.5D interposer, 3D-IC, fan-out wafer-level packaging, and silicon bridge technologies (e.g., CoWoS, EMIB, or similar).
• Support package floorplan development considering die placement, bump maps, power/ground distribution, signal escape routing, and decoupling capacitor placement.
• Perform RDL and substrate routing for high-density interconnects including microbumps, C4 bumps, TSVs, microvias, and PTH vias across multi-layer organic substrates or silicon interposers.
• Support die-level RDL routing and bump planning in coordination with ASIC physical design teams to help co-optimize the die-package interface.
• Contribute to cross-level layout co-optimization across die RDL, interposer/substrate, and PCB levels under guidance from senior engineers.
• Assist in maintaining package stack-up definitions in collaboration with SI/PI and materials engineering teams.
• Run physical verification checks (DRC, connectivity, shorts/opens) and support design closure.
• Follow and help refine package design rules and guidelines, working with OSAT partners and foundries to ensure DFM compliance.
• Collaborate with SI/PI engineers to incorporate electrical constraints into the physical layout — impedance-controlled routing, power plane optimization, and critical net shielding.
• Bachelor's degree in Electrical Engineering or a related field
• Experience identifying bugs in architecture, algorithms, functionality, and performance with strong overall debugging skills
• Experience verifying at multiple levels of logic from IP blocks to SoCs to full system testing
• 5+ years of experience in IC package layout and physical design
• Experience executing package designs from concept through tape out for multi-layer organic substrates or silicon interposers
• Hands-on experience with package layout tools such as Cadence APD/SiP, Synopsys IC Packaging, Mentor Xpedition, or equivalent
• Understanding of advanced packaging technologies: 2.5D/3D-IC, fan-out WLP, RDL, TSV, microbump, or silicon bridge interconnects
• Working knowledge of package design rules, DFM constraints, and physical verification methodologies (DRC, connectivity checks)
• Experience with bump map and ball map definition, escape routing strategies, and power/ground plane design
• Good communication skills with the ability to work effectively across design, SI/PI, and manufacturing teams
• Master's degree in Electrical or Communications Engineering or a related field
• Experience with formal verification techniques including abstraction and end-to-end checking

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