Job description

About Sandia: Sandia National Laboratories is the nation’s premier science and engineering lab for national security and technology innovation, with teams of specialists focused on cutting-edge work in a broad array of areas. Some of the main reasons we love our jobs: • Challenging work with amazing impact that contributes to security, peace, and freedom worldwide • Extraordinary co-workers • Some of the best tools, equipment, and research facilities in the world • Career advancement and enrichment opportunities • Flexible work arrangements for many positions include 9/80 (work 80 hours every two weeks, with every other Friday off) and 4/10 (work 4 ten-hour days each week) compressed workweeks, part-time work, and telecommuting (a mix of onsite work and working from home) • Generous vacation, strong medical and other benefits, competitive 401k, learning opportunities, relocation assistance and amenities aimed at creating a solid work/life balance* World-changing technologies. Life-changing careers. Learn more about Sandia at: sandia.gov *These benefits vary by job classification. What Your Job Will Be Like: We are seeking a highly motivated Digital IC Design Engineer to join a collaborative team delivering advanced ASIC solutions for mission and laboratory customers. This role focuses on translating system needs into robust, verifiable RTL through tapeout, with close coordination across analog/MEMS/photonics and physical-design partners. On any given day, you may be called on to: • Review project schedules and milestones (tapeout targets, design reviews, lab deliverables) with the PI/tech lead, identify blockers (PDK/tool updates, interface questions, verification gaps), and drive closure • Convert customer/mission needs into clear block-level specifications (performance, power, area, radiation tolerance, interfaces, testability) and maintain requirements-to-design traceability • Develop and maintain RTL (control, datapath/DSP, interfaces), integrate IP, and implement clean CDC/reset strategies and appropriate low-power/clocking techniques. • Build and extend verification environments; run regressions; analyze failures; close coverage; and perform lint, CDC, and formal checks with documented evidence for reviews • Run or coordinate synthesis and implementation handoff; review timing/power reports; debug critical paths; and iterate with physical design to meet constraints • Collaborate closely with analog/MEMS/photonics teams on mixed-signal interfaces (ADC/DAC timing, bias/control, sensor protocols) and validate behavior against system-level models • Apply knowledge of advanced integration constraints (I/O, routing, packaging, thermal, signal integrity; 2.5D/3D integration) to architecture and implementation tradeoffs • Incorporate resiliency features as required (TMR/EDAC, scrubbing, watchdogs, redundancy) and support radiation/reliability analysis and trade studies • Define scan/BIST strategy, test hooks and observability for lab bring-up, and support post-silicon debug planning and test-vector development • Maintain design documentation (ICDs, review packages) and present at peer reviews; capture decisions and action items for configuration control • Contribute to R&D efforts in advanced signal/data processing (e.g., focal-plane arrays, radiation detector readouts, neuromorphic concepts, quantum support circuits) through simulation and small test chips • Follow configuration management, data handling, and tool/PDK usage practices, coordinating with foundry/MPW schedules and internal processes as applicable Due to the nature of the work, the selected applicant must be able to work onsite. Salary Range: $102,400 - $199,700 *Salary range is estimated, and actual salary will be determined after consideration of the selected candidate's experience and qualifications, and application of any approved geographic salary differential. Qualifications We Require: • A Bachelor's degree in a relevant discipline, or an equivalent combination of directly relevant education and engineering or scientific experience that demonstrates the knowledge, skills, and ability to perform independent research and development • Ability to obtain and maintain a DOE Q clearance Qualifications We Desire: • Strong proficiency in RTL design using Verilog/SystemVerilog, including synthesizable coding practices • Experience with digital design fundamentals such as pipelining, clock-domain crossing, FSMs, datapath/control partitioning, and timing closure • Ability to use EDA toolflows for synthesis, static timing analysis (STA), linting, CDC/RDC checks, and formal verification • Solid understanding of CMOS device physics, digital logic, noise margins, and process technology scaling effects • Hands-on experience with simulation and verification using UVM or similar methodologies • Familiarity with SoC integration, bus protocols (AXI/AHB/APB), and IP block-level design. • Competency in power aware design, low power techniques (clock gating, power gating), and PPA tradeoff analysis • Competency in Radiation hardened design • Ability to read and interpret schematics, timing diagrams, and physical design constraints (SDC) • Ability to collaborate with analog, physical design, firmware, and systems teams to ensure successful chip integration and tape out About Our Team: The Mixed-Signal ASIC/SoC Products Department specializes in developing analog and digital integrated circuits (IC) for a variety of applications that require high reliability, high performance or specialized integrated circuits. The department develops a wide range of Application Specific Integrated Circuits (ASICs) for a variety of government applications. Circuit designs include read-out electronics, data acquisition, information processing, encryption/decryption, radiation-hardened electronics, trusted computing, and control circuit applications. Customers include DOE weapons systems, satellite systems, the intelligence community, Army, Air Force, and commercial industry. Mission success is assured by employing disciplined design methodologies and state-of-the-art computer aided engineering (CAE) tools. Posting Duration: This posting will be open for application submissions for a minimum of three (3) calendar days, including the 'posting date'. Sandia reserves the right to extend the posting date at any time. Security Clearance: Sandia is required by DOE to conduct a pre-employment drug test and background review that includes checks of personal references, credit, law enforcement records, and employment/education verifications. Applicants for employment need to be able to obtain and maintain a DOE Q-level security clearance, which requires U.S. citizenship. If you hold more than one citizenship (i.e., of the U.S. and another country), your ability to obtain a security clearance may be impacted. Applicants offered employment with Sandia are subject to a federal background investigation to meet the requirements for access to classified information or matter if the duties of the position require a DOE security clearance. Substance abuse or illegal drug use, falsification of information, criminal activity, serious misconduct or other indicators of untrustworthiness can cause a clearance to be denied or terminated by DOE, resulting in the inability to perform the duties assigned and subsequent termination of employment. EEO: All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, or veteran status and any other protected class under state or federal law. NNSA Requirements for MedPEDs: If you have a Medical Portable Electronic Device (MedPED), such as a pacemaker, defibrillator, drug-releasing pump, hearing aids, or diagnostic equipment and other equipment for measuring, monitoring, and recording body functions such as heartbeat and brain waves, if employed by Sandia National Laboratories you may be required to comply with NNSA security requirements for MedPEDs. If you have a MedPED and you are selected for an on-site interview at Sandia National Laboratories, there may be additional steps necessary to ensure compliance with NNSA security requirements prior to the interview date. Job ID: 697824 Job Family: RD Regular/Temporary Position: R Full/Part-Time Status: F

Requirements

Must-haves

On any given day, you may be called on to:
Review project schedules and milestones (tapeout targets, design reviews, lab deliverables) with the PI/tech lead, identify blockers (PDK/tool updates, interface questions, verification gaps), and drive closure
Convert customer/mission needs into clear block-level specifications (performance, power, area, radiation tolerance, interfaces, testability) and maintain requirements-to-design traceability
Develop and maintain RTL (control, datapath/DSP, interfaces), integrate IP, and implement clean CDC/reset strategies and appropriate low-power/clocking techniques.
Build and extend verification environments; run regressions; analyze failures; close coverage; and perform lint, CDC, and formal checks with documented evidence for reviews
Run or coordinate synthesis and implementation handoff; review timing/power reports; debug critical paths; and iterate with physical design to meet constraints
Collaborate closely with analog/MEMS/photonics teams on mixed-signal interfaces (ADC/DAC timing, bias/control, sensor protocols) and validate behavior against system-level models
Apply knowledge of advanced integration constraints (I/O, routing, packaging, thermal, signal integrity; 2.5D/3D integration) to architecture and implementation tradeoffs
Incorporate resiliency features as required (TMR/EDAC, scrubbing, watchdogs, redundancy) and support radiation/reliability analysis and trade studies
Define scan/BIST strategy, test hooks and observability for lab bring-up, and support post-silicon debug planning and test-vector development
Maintain design documentation (ICDs, review packages) and present at peer reviews; capture decisions and action items for configuration control
Contribute to R&D efforts in advanced signal/data processing (e.g., focal-plane arrays, radiation detector readouts, neuromorphic concepts, quantum support circuits) through simulation and small test chips
Follow configuration management, data handling, and tool/PDK usage practices, coordinating with foundry/MPW schedules and internal processes as applicable
Due to the nature of the work, the selected applicant must be able to work onsite.
$102,400 - $199,700
Ability to obtain and maintain a DOE Q clearance
Strong proficiency in RTL design using Verilog/SystemVerilog, including synthesizable coding practices
Experience with digital design fundamentals such as pipelining, clock-domain crossing, FSMs, datapath/control partitioning, and timing closure
Ability to use EDA toolflows for synthesis, static timing analysis (STA), linting, CDC/RDC checks, and formal verification
Solid understanding of CMOS device physics, digital logic, noise margins, and process technology scaling effects
Hands-on experience with simulation and verification using UVM or similar methodologies
Familiarity with SoC integration, bus protocols (AXI/AHB/APB), and IP block-level design.
Competency in power aware design, low power techniques (clock gating, power gating), and PPA tradeoff analysis
Competency in Radiation hardened design

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401k