Job description

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: You will be responsible for the front end design and verification of design blocks for these cores. Specific duties will include, but are not limited to architecture definition, logic design, synthesis, constraint development; design verification through simulation, formal verification, along with analysis of timing from the physical implementation. You will design logic blocks from systems requirements documents and will simulate and debug designs with Verilog simulation. Familiarity with entire ASIC design and implementation flow. · Ability to work independently as well as part of a large team spanning multiple geographies. · Education: BS/MS in Electrical or Computer Engineering or equivalent · Bachelors and 8 years of related experience; or Masters degree and 6 years of related experience · Experience with complete ASIC or standard product implementation flow from RTL synthesis, timing analysis / closure. · Requires proficiency with the following design tools / flows: · TCL/Perl scripting · Synthesis experience with either Synopsys Design Compiler/ DC topo or Cadence RTL compiler · Timing analysis experience with Primetime for high frequency designs and advanced technology nodes/libraries · Understanding of liberty LIB models for timing · Formal verification (Synopsys Formality / Cadence Conformal) · Spyglass Lint · Power analysis of RTL and gate level netlists · Familiarity with DFT (design for test) and scan methodology · Version control (svn, git, etc) Compensation and Benefits The annual base salary range for this position is USD 121,900.00 To USD 195,000.00 As a valued member of our team, you ll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company s growth. All subject to relevant plan documents and award agreements. Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence. Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law. If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Requirements

Must-haves

If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)
If you already have a Candidate Account, please Sign-In before you apply.
Ability to work independently as well as part of a large team spanning multiple geographies.
Education: BS/MS in Electrical or Computer Engineering or equivalent
Bachelors and 8 years of related experience; or Masters degree and 6 years of related experience
Experience with complete ASIC or standard product implementation flow from RTL synthesis, timing analysis / closure.
Requires proficiency with the following design tools / flows:
TCL/Perl scripting
Synthesis experience with either Synopsys Design Compiler/ DC topo or Cadence RTL compiler
Timing analysis experience with Primetime for high frequency designs and advanced technology nodes/libraries
Understanding of liberty LIB models for timing
Formal verification (Synopsys Formality / Cadence Conformal)
Spyglass Lint
Power analysis of RTL and gate level netlists
Familiarity with DFT (design for test) and scan methodology
Version control (svn, git, etc)

Nice-to-haves

None flagged.

Application prep

Use the role’s language and application details while tailoring your materials.

Platform: workday
Effort: long

Benefits

Benefits detected in the listing.

Dental

Vision

401(K)